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Field Programmable Logic and Applications

FPL

B

CORE rank

CORE rank (raw)

B

Fields of research

Computer Systems Engineering

Papers indexed

3,233

1994–2025

Papers per year

1994182 peak2025

FPL papers

3,233 records sourced from DBLP. Search titles, filter by year, sort by recency.

YearTitleAuthors
2009Multi-terminal BDD synthesis and applications.Petr Mikusek
2009Automatic generation of FPGA hardware accelerators using a domain specific language.Ricardo Menotti, Joo M. P. Cardoso, Marcio Merino Fernandes, Eduardo Marques
2009Improving the quality of a Physical Unclonable Function using configurable Ring Oscillators.Abhranil Maiti, Patrick Schaumont
2009A multi-FPGA architecture for stochastic Restricted Boltzmann Machines.Daniel Le Ly, Paul Chow
2009Cooperative multithreading in dynamically reconfigurable systems.Enno Lbbers, Marco Platzner
2009A dynamically reconfigurable parallel pixel processing system.Daniel Llamocca, Marios S. Pattichis, G. Alonzo Vera
2009Optimising designs by combining model-based and pattern-based transformations.Qiang Liu, Tim Todman, Jos Gabriel de Figueiredo Coutinho, Wayne Luk, George A. Constantinides
2009Run-time Partial Reconfiguration speed investigation and architectural design space exploration.Ming Liu, Wolfgang Kuehn, Zhonghai Lu, Axel Jantsch
2009An FPGA based verification platform for HyperTransport 3.x.Heiner Litz, Holger Frning, Maximilian Thrmer, Ulrich Brning
2009Operation scheduling for FPGA-based reconfigurable computers.Colin Yu Lin, Ngai Wong, Hayden Kwok-Hay So
2009Replace: An incremental placement algorithm for field programmable gate arrays.David Leong, Guy G. Lemieux
2009Fast critical sections via thread scheduling for FPGA-based multithreaded processors.Martin Labrecque, J. Gregory Steffan
2009A novel SRAM-based FPGA architecture for efficient TMR fault tolerance support.Konstantinos Kyriakoulakos, Dionisios N. Pnevmatikatos
2009Macs: A Minimal Adaptive routing circuit-switched architecture for scalable and parametric NoCs.Rohit Kumar, Ann Gordon-Ross
2009Pipeline implementation of the 128-bit block cipher CLEFIA in FPGA.Tomasz Kryjak, Marek Gorgon
2009Design space exploration of reconfigurable systems for calculating flying object's optimal noise reduction paths.Dimitrios Kontos, Ioannis Papaefstathiou, Dionisios N. Pnevmatikatos
2009Real-time processing of local contrast enhancement on FPGA.Kentaro Kokufuta, Tsutomu Maruyama
2009A highly scalable Restricted Boltzmann Machine FPGA implementation.Sang Kyun Kim, Lawrence C. McAfee, Peter Leonard McMahon, Kunle Olukotun
2009IP protection in Partially Reconfigurable FPGAs.Krzysztof Kepa, Fearghal Morgan, Krzysztof Kosciuszkiewicz
2009Performance comparison of single-precision SPICE Model-Evaluation on FPGA, GPU, Cell, and multi-core processors.Nachiket Kapre, Andr DeHon
2009Low power techniques for Motion Estimation hardware.Caglar Kalaycioglu, Onur Can Ulusel, Ilker Hamzaoglu
2009Enhanced gradient-based motion vector coprocessor.Guillermo Botella Juan, Antonio Garca Ros, Uwe Meyer-Bse, Manuel Rodrguez, Mara C. Molina, Lus Parrilla Roure
2009A new deadlock-free fault-tolerant routing algorithm for NoC interconnections.Slavisa Jovanovic, Camel Tanougast, Serge Weber, Christophe Bobda
2009Exploring reconfigurable architectures for explicit finite difference option pricing models.Qiwei Jin, David B. Thomas, Wayne Luk
2009Reconfigurable fault tolerance: A framework for environmentally adaptive fault mitigation in space.Adam Jacobs, Alan D. George, Grzegorz Cieslewski
1,5261,550 of 3,233← PreviousNext →

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