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Field Programmable Logic and Applications

FPL

B

CORE rank

CORE rank (raw)

B

Fields of research

Computer Systems Engineering

Papers indexed

3,233

1994–2025

Papers per year

1994182 peak2025

FPL papers

3,233 records sourced from DBLP. Search titles, filter by year, sort by recency.

YearTitleAuthors
2009Optimal runtime reconfiguration strategies for systolic arrays.Arpith C. Jacob, Jeremy D. Buhler, Roger D. Chamberlain
2009A novel SEU, MBU and SHE handling strategy for Xilinx Virtex-4 FPGAs.Xabier Iturbe, Mikel Azkarate-askasua, Imanol Martinez, Jon Prez, Armando Astarloa
2009Modularizing flux limiter functions for a Computational Fluid Dynamics accelerator on FPGAs.Kenta Inakagata, Hirokazu Morishita, Yasunori Osana, Naoyuki Fujita, Hideharu Amano
2009Globally optimal time-multiplexing in inter-FPGA connections for accelerating multi-FPGA systems.Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura
2009An efficient reconfigurable architecture to implement dense stereo vision algorithm using high-level synthesis.Mario Alberto Ibarra-Manzano, Michel Devy, Jean-Louis Boizard, Pierre Lacroix, Jean-Yves Fourniols
2009Comparing fine-grained performance on the Ambric MPPA against an FPGA.Brad L. Hutchings, Brent E. Nelson, Stephen West, Reed Curtis
2009Clock gating architectures for FPGA power reduction.Safeen Huda, Muntasir Mallick, Jason Helge Anderson
2009Run-time resource management in fault-tolerant network on reconfigurable chips.Mohammad Hosseinabady, Jos L. Nez-Yez
2009Design and evaluation of an energy-efficient dynamically reconfigurable architecture for wireless sensor nodes.Heiko Hinkelmann, Peter Zipf, Manfred Glesner
2009Dynamic reconfiguration system for real-time video processing.Saya Hinaga, Yoshiki Yamaguchi, Tetsuhiko Yao, Tohru Kawabe
2009FPGA partial reconfiguration via configuration scrubbing.Jonathan Heiner, Benjamin Sellers, Michael J. Wirthlin, Jeff Kalb
2009Multigigabit network traffic processing.Jiri Halak
2009FPGA-implementation of Time-Multiplexed Multiple Constant Multiplication based on carry-save arithmetic.Roberto Gutirrez, Javier Valls, Asuncion Perez-Pascual
2009FPGA support for satellite computations of hyper spectral images.Carlos Gonzlez, Daniel Mozos, Javier Resano
2009Star-Wheels Network-on-Chip featuring a self-adaptive mixed topology and a synergy of a circuit - and a packet-switching communication protocol.Diana Ghringer, Bin Liu, Michael Hbner, Jrgen Becker
2009Emulating Spiking Neural Networks for edge detection on FPGA hardware.Brendan P. Glackin, Jim Harkin, T. Martin McGinnity, Liam P. Maguire, Qingxiang Wu
2009Dynamic reconfigurable mixed-signal architecture for safety critical applications.Romuald Girardey, Michael Hbner, Jrgen Becker
2009Program-driven fine-grained power management for the reconfigurable mesh.Heiner Giefers, Marco Platzner
2009An approach to system-wide fault tolerance for FPGAs.Jano Gebelein, Heiko Engel, Udo Kebschull
2009Synthesis of the SR programming language for complex FPGAs.Nick Gasson, Neil C. Audsley
2009Efficient AES S-boxes implementation for non-volatile FPGAs.Lubos Gaspar, Milos Drutarovsk, Viktor Fischer, Nathalie Bochard
2009CREMA: A coarse-grain reconfigurable array with mapping adaptiveness.Fabio Garzia, Waqar Hussain, Jari Nurmi
2009Hardware implementation of MPI_Barrier on an FPGA cluster.Shanyuan Gao, Andrew G. Schmidt, Ron Sass
2009CNP: An FPGA-based processor for Convolutional Networks.Clment Farabet, Cyril Poulet, Jefferson Y. Han, Yann LeCun
2009Static versus scheduled interconnect in Coarse-Grained Reconfigurable Arrays.Brian Van Essen, Aaron Wood, Allan Carroll, Stephen Friedman, Robin Panda, Benjamin Ylvisaker, Carl Ebeling, Scott Hauck
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