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Field Programmable Logic and Applications

FPL

B

CORE rank

CORE rank (raw)

B

Fields of research

Computer Systems Engineering

Papers indexed

3,233

1994–2025

Papers per year

1994182 peak2025

FPL papers

3,233 records sourced from DBLP. Search titles, filter by year, sort by recency.

YearTitleAuthors
2009An ASIC perspective on FPGA optimizations.Andreas Ehliar, Dake Liu
2009A self-reconfiguring architecture supporting multiple objective functions in genetic algorithms.Charalampos Effraimidis, Kyprianos Papadimitriou, Apostolos Dollas, Ioannis Papaefstathiou
2009FPGA accelerating three QR decomposition algorithms in the unified pipelined framework.Yong Dou, Jie Zhou, Xiaoyang Chen, Yuanwu Lei, Jinbo Xu
2009Large multipliers with fewer DSP blocks.Florent de Dinechin, Bogdan Pasca
2009Generating high-performance custom floating-point pipelines.Florent de Dinechin, Cristian Klein, Bogdan Pasca
2009Using C-to-gates to program streaming image processing kernels efficiently on FPGAs.Kristof Denolf, Stephen Neuendorffer, Kees A. Vissers
2009Modeling post-techmapping and post-clustering FPGA circuit depth.Joydip Das, Steven J. E. Wilton, Philip Heng Wai Leong, Wayne Luk
2009Customizable domain-specific computing.Jason Cong
2009Optimizing the SUSAN corner detection algorithm for a high speed FPGA implementation.Christopher Claus, Robert Huitl, Joachim Rausch, Walter Stechele
2009A FPGA based coprocessor for gene finding using Interpolated Markov Model (IMM).Grigorios Chrysos, Euripides Sotiriades, Ioannis Papaefstathiou, Apostolos Dollas
2009An FPGA-based embedded wideband audio codec system.Chang Choo, Bhavya Bambhania, Woon Seob So, In Ki Hwang, Do Young Kim
2009Efficient particle-pair filtering for acceleration of molecular dynamics simulation.Matt Chiu, Martin C. Herbordt
2009Improving the memory footprint and runtime scalability of FPGA CAD algorithms.Scott Y. L. Chin, Steven J. E. Wilton
2009An analytical model relating FPGA architecture and place and route runtime.Scott Y. L. Chin, Steven J. E. Wilton
2009A low cost reconfigurable soft processor for multimedia applications: Design synthesis and programming model.Sai Rahul Chalamalasetti, Wim Vanderbauwhede, Sohan Purohit, Martin Margala
2009Using 3D integration technology to realize multi-context FPGAs.Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Maurizio Skerlj, Philip Brisk, Yusuf Leblebici, Paolo Ienne
2009Acceleration of complex algorithms on a fast reconfigurable embedded system on Spartan-3.Enrique Cant, Mariano Fons, Mariano Lpez-Garca, Rafael Ramos-Lara
2009Implementation of a reconfigurable Fast Fourier Transform application to digital terrestrial television broadcasting.Florent Camarda, Jean-Christophe Prvotet, Fabienne Nouvel
2009Secure FPGA technologies and techniques.An Braeken, Serge Kubera, Frederik Trouillez, Abdellah Touhafi, Nele Mentens, Jo Vliegen
2009FPGA challenges and opportunities at 40nm and beyond.Vaughn Betz
2009Proteus: An architectural synthesis tool based on the stream programming paradigm.Nikolaos Bellas, Sek M. Chai, Malcolm Dwyer, Dan Linzmeier, Abelardo Lpez-Lagunas
2009Off-line placement of hardware tasks on FPGA.Ikbel Belaid, Fabrice Muller, Maher Benjemaa
2009RISPP: A run-time adaptive reconfigurable embedded processor.Lars Bauer, Muhammad Shafique, Jrg Henkel
2009Soft errors in Flash-based FPGAs: Analysis methodologies and first results.Niccol Battezzati, Filomena Decuzzi, Luca Sterpone, Massimo Violante
2009Sharf: An FPGA-based customizable processor architecture.Cem Savas Bassoy, Henning Manteuffel, Friedrich Mayer-Lindenberg
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