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Field Programmable Logic and Applications

FPL

B

CORE rank

CORE rank (raw)

B

Fields of research

Computer Systems Engineering

Papers indexed

3,233

1994–2025

Papers per year

1994182 peak2025

FPL papers

3,233 records sourced from DBLP. Search titles, filter by year, sort by recency.

YearTitleAuthors
2007Novel Multi-Layer floorplanning for Heterogeneous FPGAs.Love Singhal, Elaheh Bozorgzadeh
2007Efficient FPGA-based multipliers for F_3^97 and F_3^(6*97).Jamshid Shokrollahi, Elisa Gorla, Christoph Puttmann
2007Analysis of Kernel Effects on Optimisation Mismatch in Cache Reconfiguration.John Shield, Peter Sutton, Philip Machanick
2007Dynamic Cache Switching in Reconfigurable Embedded Systems.John Shield, Peter Sutton, Philip Machanick
2007Implementation of a barotropic operator for ocean model simulation using a reconfigurable machine.Sayaka Shida, Yuichiro Shibata, Kiyoshi Oguri, Duncan A. Buell
2007artNoC - A Novel Multi-Functional Router Architecture for Organic Computing.Christian Schuck, Stefan Lamparth, Jrgen Becker
2007A Time-Triggered Network-on-Chip.Martin Schoeberl
2007Characterizing Effective Memory Bandwidth of Designs with Concurrent High-Performance Computing Cores.Andrew G. Schmidt, Ron Sass
2007Dynamic Partial FPGA Reconfiguration in a Prototype Microprocessor System.Kai Schleupen, Scott Lekuch, Ryan Mannion, Zhi Guo, Walid A. Najjar, Frank Vahid
2007A Software Defined Radio Application Utilizing Modern FPGAs and NoC Interconnects.Graham Schelle, Jeff Fifield, Dirk Grunwald
2007REDEFINE: Architecture of a SoC Fabric for Runtime Composition of Computation Structures.A. N. Satrawala, Keshavan Varadarajan, Mythri Alle, S. K. Nandy, Ranjani Narayan
2007Automatic Software Hardware Co-Design for Reconfigurable Computing Systems.Proshanta Saha
2007A Run-time Reconfigurable Processor for Video Motion Estimation.Miguel Ribeiro, Leonel Sousa
2007Run-time Partial Reconfiguration for Removal, Placement and Routing on the Virtex-II-Pro.Stefan Raaijmakers, Stephan Wong
2007Embedded Programmable Logic Core Enhancements for System Bus Interfaces.Bradley R. Quinton, Steven J. E. Wilton
2007RLS Lattice Algorithm with Order Probability Evaluation as an Accelerator for the Microblaze Processor.Zdenek Pohl, Milan Tich
2007Time Predictable CPU and DMA Shared Memory Access.Christof Pitter, Martin Schoeberl
2007Equivalence Verification of FPGA and Structured ASIC Implementations.Joachim Pistorius, Mike Hutton, Jay Schleicher, Mihail Iotov, Enoch Julias, Kumara Tharmalingam
2007Effective Automatic Memory Allocation Algorithm Based on Schedule Length in Cycles in a Novel C to FPGA Compiler.Kristopher D. Peterson, Justin L. Tripp
2007On-line Routing of Reconfigurable Functions for Future Self-Adaptive Systems - Investigations within the THER Project.Katarina Paulsson, Michael Hbner, Jrgen Becker, Jean-Marc Philippe, Christian Gamrat
2007Implementation of a Virtual Internal Configuration Access Port (JCAP) for Enabling Partial Self-Reconfiguration on Xilinx Spartan III FPGAs.Katarina Paulsson, Michael Hbner, Gnther Auer, Michael Dreschmann, Jrgen Becker
2007Soft-Hard 3D FD-TD Solver for Non Destructive Evaluation.Fernando Pardo, Paula Lpez, Diego Cabello
2007A Novel Event Based Simulation Algorithm for Sequential Digital Circuit Simulation.Karthick Parashar, Nitin Chandrachoodan
2007Self-Healing Circuits for Space-Applications.Thomas Panhofer, Martin Delvai
2007Wirelength Prediction for FPGAs.Audip Pandit, Ali Akoglu
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