| 2007 | A Behavioral Synthesis Approach for Distributed Memory FPGA Architectures. | Ashutosh Pal, M. Balakrishnan |
| 2007 | Automatic Accuracy-Guaranteed Bit-Width Optimization for Fixed and Floating-Point Systems. | William George Osborne, Ray C. C. Cheung, Jos Gabriel F. Coutinho, Wayne Luk, Oskar Mencer |
| 2007 | Layered Approach to Instrinsic Evolvable Hardware Using Direct Bistream Manipulation of VIRTEX II Pro Devices. | Rashad S. Oreifej, Rawad N. Al-Haddad, Heng Tan, Ronald F. DeMara |
| 2007 | Dynamic Voltage Scaling in a FPGA-based System-on-Chip. | Jos L. Nez-Yez, Vassilios A. Chouliaras, Jiri Gaisler |
| 2007 | A Multi Objective GA based Physical Placement Algorithm for Heterogeneous Dynamically Reconfigurable Arrays. | Ioannis Nousias, Sami Khawam, Mark Milward, Mark Muir, Tughrul Arslan |
| 2007 | Power Reduction in Network Equipment through Adaptive Partial Reconfiguration. | Juanjo Noguera, Irwin O. Kennedy |
| 2007 | Efficient External Memory Interface for Multi-processor Platforms Realized on FPGA Chips. | Hristo Nikolov, Todor P. Stefanov, Ed F. Deprettere |
| 2007 | L4: An FPGA-Based Accelerator for Detailed Maze Routing. | John A. Nestor, Jeremy Lavine |
| 2007 | Mapping A VLIWxSIMD Processor on an FPGA: Scalability and Performance. | Micha Nelissen, Kees van Berkel, Sergei Sawitzki |
| 2007 | Performance Modeling of 2D Cellular Automata on FPGA. | S. Murtaza, Alfons G. Hoekstra, Peter M. A. Sloot |
| 2007 | Microarchitectural Enhancements for Configurable Multi-Threaded Soft Processors. | Roger Moussali, Nabil Ghanem, Mazen A. R. Saghir |
| 2007 | Efficient Priority-Queue Data Structure for Hardware Implementation. | Andrew Morton, Jeffrey Liu, Insop Song |
| 2007 | Design Space Exploration of the European Option Benchmark Using HyperStreams. | Gareth W. Morris, Matthew Aubury |
| 2007 | Exploiting Analog and Digital Reconfiguration for Smart Sensor Interfacing. | Diego Pedro Morales, Antonio Garca, Alberto J. Palma, Antonio Martnez-Olmos, Encarnacin Castillo |
| 2007 | Discrete Event Simulation of Molecular Dynamics with Configurable Logic. | Josh Model, Martin C. Herbordt |
| 2007 | Virtualization on the Tartan Reconfigurable Architecture. | Mahim Mishra, Seth Copen Goldstein |
| 2007 | RIC Fast Adder and its Set Tolerant Implementation in FPGAs. | Eduardo Mesquita, Helen Franck, Luciano Volcan Agostini, Jos Lus Gntzel |
| 2007 | Aggressive Loop Pipelining for Reconfigurable Architectures. | Ricardo Menotti, Eduardo Marques, Joo M. P. Cardoso |
| 2007 | A Quantitative Prediction Model for Hardware/Software Partitioning. | Roel Meeuws, Yana Yankova, Koen Bertels, Georgi Gaydadjiev, Stamatis Vassiliadis |
| 2007 | An FPGA Implementation of Multiple Sequence Alignment Based on Carrillo-Lipman Method. | Shingo Masuno, Tsutomu Maruyama, Yoshiki Yamaguchi, Akihiko Konagaya |
| 2007 | H.264/AVC In-Loop De-Blocking Filter Targeting a Dynamically Reconfigurable Instruction Cell Based Architecture. | Adam Major, Ioannis Nousias, Sami Khawam, Mark Milward, Ying Yi, Mark Muir, Tughrul Arslan |
| 2007 | A generalized and unified SPFD-based rewiring technique. | Pongstorn Maidee, Kia Bazargan |
| 2007 | NoC Implementation in FPGA Using Torus Topology. | Angelo Kuti Lusala, Philippe Manet, Bertrand Rousseau, Jean-Didier Legat |
| 2007 | ReconOS: An RTOS supporting Hard- and Software Threads. | Enno Lbbers, Marco Platzner |
| 2007 | Efficient mapping of a Kalman filter into an FPGA using Taylor Expansion. | Yang Liu, Christos-Savvas Bouganis, Peter Y. K. Cheung |