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Field Programmable Logic and Applications

FPL

B

CORE rank

CORE rank (raw)

B

Fields of research

Computer Systems Engineering

Papers indexed

3,233

1994–2025

Papers per year

1994182 peak2025

FPL papers

3,233 records sourced from DBLP. Search titles, filter by year, sort by recency.

YearTitleAuthors
2007An Efficient Implementation of a 2D DWT on FPGA.Michael Wisdom, Peter Lee
2007Incremental Fault Emulation.Jan Torben Weinkopf, Klaus Harbich, Erich Barke
2007Adventures with a Reconfigurable Research Platform.John Wawrzynek
2007A Hardware Algorithm for the Minimum p-Quasi Clique Cover Problem.Shuichi Watanabe, Junji Kitamichi, Kenichi Kuroda
2007A Temporal Correlation Based Port Combination Methodology for Networks-on-chip on Reconfigurable Systems.Daihan Wang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
2007Monte Carlo Logarithmic Number System for Model Predictive Control.Panagiotis D. Vouzis, Caroline Collange, Mark G. Arnold, Mayuresh V. Kothare
2007Improving Annealing Via Directed Moves.Kristofer Vorwerk, Andrew A. Kennings, Jonathan W. Greene, Doris T. Chen
2007Dynamically reconfigurable dataflow architecture for high-performance digital signal processing on multi-FPGA platforms.Sven-Ole Voigt, Thomas Teufel
2007Router Design for Application Specific Networks-on-Chip on Reconfigurable Systems.Mrio P. Vstias, Horcio C. Neto
2007A Load/Store Unit for a Memcpy Hardware Accelerator.Stamatis Vassiliadis, Filipa Duarte, Stephan Wong
2007An area-efficient alternative to adaptive median filtering in FPGAs.Zdenek Vascek, Luks Sekanina
2007Redefining the FPGA for the Next Generation.Steve Trimberger
2007A Pipeline Implementation of a Watershed Algorithm on FPGA.Dang Ba Khac Trieu, Tsutomu Maruyama
2007Compression system for the phonocardiographic signal.F. Javier Toledo-Moreo, A. Legaz-Cano, J. Javier Martnez-lvarez, Juan Martnez-Alajarn, Ramn Ruiz Merino
2007MORPHEUS: Heterogeneous Reconfigurable Computing.Florian Thoma, Matthias Khnle, Philippe Bonnot, Elena Moscu Panainte, Koen Bertels, Sebastian Goller, Axel Schneider, Stphane Guyetant, Eberhard Schler, Klaus D. Mller-Glaser, Jrgen Becker
2007Applying Out-of-Core QR Decomposition Algorithms on FPGA-Based Systems.Yi-Gang Tai, Chia-Tien Dan Lo, Kleanthis Psarris
2007A Hybrid Reconfigurable Cluster-on-Chip Architecture With Message Passing Interface For Image Processing Applications.Irfan Syed, John A. Williams, Neil W. Bergmann
2007An FPGA Approach to Quantifying Coherence Traffic Efficiency on Multiprocessor Systems.Taeweon Suh, Shih-Lien Lu, Hsien-Hsin S. Lee
2007A novel motion estimation power reduction technique.Graeme Robert Stewart, David Renshaw, Martyn Riley
2007Hybridthreads Compiler: Generation of Application Specific Hardware Thread Cores from C.Jim Stevens
2007A high throughput area time efficient pseudo uniform random number generator based on the TT800 algorithm.Vinay Sriram, David Kearney
2007A Radio Astronomy Correlator Optimized for the XILINX VIRTEX-4 SX FPGA.Ludovico de Souza, John D. Bunton, Duncan Campbell-Wilson, Roger J. Cappallo, Barton B. Kincaid
2007Implementation of a 2-D 8x8 IDCT on the Reconfigurable Montium Core.Lodewijk T. Smit, Gerard K. Rauwerda, Albert Molderink, Pascal T. Wolkotte, Gerard J. M. Smit
2007Statistical Generic And Chip-Specific Skew Assignment for Improving Timing Yield of FPGAs.Satish Sivaswamy, Kia Bazargan
2007Exploring Alternative 3D FPGA Architectures: Design Methodology and CAD Tool Support.Kostas Siozios, Kostas Sotiriadis, Vasilis F. Pavlidis, Dimitrios Soudris
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