| 2007 | A Variable Grain Logic Cell Architecture for Reconfigurable Logic Cores. | Motoki Amagasaki, Ryoichi Yamaguchi, Kazunori Matsuyama, Masahiro Iida, Toshinori Sueyoshi |
| 2007 | System-level Modelling and Analysis of Embedded Reconfigurable Cores for Wireless Systems. | Ali Ahmadinia, Balal Ahmad, Ahmet T. Erdogan, Tughrul Arslan |
| 2006 | Identifying FPGA IP-Cores Based on Lookup Table Content Analysis. | Daniel Ziener, Stefan Assmus, Jrgen Teich |
| 2006 | High-Performance and Parameterized Matrix Factorization on FPGAs. | Ling Zhuo, Viktor K. Prasanna |
| 2006 | A Congestion Driven Placement Algorithm for FPGA Synthesis. | Yue Zhuo, Hao Li, Saraju P. Mohanty |
| 2006 | The Darpa Multiple Precision Arithmetic Benchmark on a Reconfigurable Computer. | Cao Zhang, Duncan A. Buell, Allen Michalski |
| 2006 | Executing Hardware as Parallel Software for Picoblaze Networks. | Pengyuan Yu, Patrick Schaumont |
| 2006 | An FPGA Implementation of High Throughput Stochastic Simulator for Large-Scale Biochemical Systems. | Masato Yoshimi, Yasunori Osana, Yow Iwaoka, Yuri Nishikawa, Toshinori Kojima, Akira Funahashi, Noriko Hiroi, Yuichiro Shibata, Naoki Iwanaga, Hiroaki Kitano, Hideharu Amano |
| 2006 | An FPGA-Based Electronic Cochlea with Dual Fixed-Point Arithmetic. | C. K. Wong, Philip Heng Wai Leong |
| 2006 | Parsifal: A Generic and Configurable Fault Emulation Environment with Non-Classical Fault Models. | Jan Torben Weinkopf, Klaus Harbich, Erich Barke |
| 2006 | Multi Stream Cipher Architecture for Reconfigurable System-on-Chip. | Chin Mun Wee, Peter R. Sutton, Neil W. Bergmann, John A. Williams |
| 2006 | A Reconfiguration Speed Adjustment Technique for ORGAs with a Holographic Memory. | Minoru Watanabe, Fuminori Kobayashi |
| 2006 | Prototyping a Globally Asynchronous Locally Synchronous Network-On-Chip on a Conventional FPGA Device Using Synchronous Design Tools. | Xin Wang, Tapani Ahonen, Jari Nurmi |
| 2006 | A Generic Network-on-Chip Architecture for Reconfigurable Systems: Implementation and Evaluation. | Mrio P. Vstias, Horcio C. Neto |
| 2006 | Automated Conversion From Lut-Based FPGAs to LUT-Based MPGAs. | Francisco-Javier Veredas, Hans-Jrg Pfleiderer |
| 2006 | FPGA Based Acceleration of the Linpack Benchmark: A High Level Code Transformation Approach. | Kieron Turkington, Konstantinos Masselos, George A. Constantinides, Philip Heng Wai Leong |
| 2006 | Implementation of a Parallel and Pipelined Watershed Algorithm on FPGA. | Dang Ba Khac Trieu, Tsutomu Maruyama |
| 2006 | Area-Efficient Implementation of a Pulse-Mode Neuron Model. | Csar Torres-Huitzil |
| 2006 | Skin Color Detection for Real Time Mobile Applications. | F. Javier Toledo, J. Javier Martnez, F. Javier Garrigs, Jos M. Ferrndez, V. Rodellar |
| 2006 | A-B Nodes Classification for Power Estimation. | Elias Todorovich, Eduardo I. Boemo |
| 2006 | Non-Uniform Random Number Generation Through Piecewise Linear Approximations. | David B. Thomas, Wayne Luk |
| 2006 | Software-Oriented Approach to Hardware-Software Co-Simulation for FPGA-Based Risc Extensible Processor. | K. S. Tham, Douglas L. Maskell |
| 2006 | A Segmentation Model for Partial Run-Time Reconfiguration. | Mohamed Taher, Tarek A. El-Ghazawi |
| 2006 | Placing Functionality in Fault-Tolerant Hardware/Software Reconfigurable Networks. | Thilo Streichert |
| 2006 | Architecture Exploration and Tools for Pipelined Coarse-Grained Reconfigurable Arrays. | Florian Stock, Andreas Koch |