Field Programmable Logic and Applications

FPL

CORE rank

CORE rank (raw)

Fields of research

Computer Systems Engineering

Papers indexed

3,233

1994–2025

Best Computer Systems Engineering conferences

Papers per year

1994182 peak2025

Most published authors

FPL papers

3,233 records sourced from DBLP. Search titles, filter by year, sort by recency.

Year	Title	Authors
2007	Fault Models and Yield Analysis for QCA-based PLAs.	Michael Crocker, Michael T. Niemier, Xiaobo Sharon Hu
2007	GENDIV - A Hardware Algorithm for Intron and Exon String Detection in DNA Chains.	Octavian Cret, Zsolt Mathe, Paul Ciobanu, Sonia Marginean, Cristian Lelutiu
2007	Evolutionary Search Applied to Reconfigurable Analogue Control.	Kester Dean Clegg, Susan Stepney, Tim Clarke
2007	High Level Power Optimization by Type Inference on the Generation of Application Specific Circuits on FPGAs.	Jos M. Claver, Germn Len
2007	A Reprogrammable and Scalable Multimedia Traffic Generator/Monitor on FPGA.	Jos M. Claver, P. Agust, Germn Len, Manel Canseco
2007	On the feasibility of early routing capacitance estimation for FPGAs.	Jonathan A. Clarke, George A. Constantinides, Peter Y. K. Cheung
2007	Improving Timing-Driven FPGA Packing With Physical Information.	Doris T. Chen, Kristofer Vorwerk, Andrew A. Kennings
2007	Efficient Modeling and Floorplanning of Embedded-FPGA Fabric.	Sumanta Chaudhuri, Jean-Luc Danger, Sylvain Guilley
2007	SoPC architecture for a Key Point Detector.	Harding Djakou Chati, Felix Mhlbauer, Tim Braun, Christophe Bobda, Karsten Berns
2007	Intellectual Property Protection of HDL IP Cores Through Automated Sognature Hosting.	Encarnacin Castillo, Luis Parrilla, Antonio Garca, Uwe Meyer-Bse, Antonio Lloris-Ruz
2007	An FPGA Based Memory Efficient Shared Buffer Implementation.	Dwayne Burns, Ciaran Toal, Kieran McLaughlin, Sakir Sezer, Mike Hutton, Kevin Cackovic
2007	A Method for Fast Hardware Specialization at run-time.	Karel Bruneel, Peter Bertels, Dirk Stroobandt
2007	An OCM based shared Memory controller for Virtex 4.	Bas Breijer, Filipa Duarte, Stephan Wong
2007	Circuit Switched Run-Time Adaptive Network-on-Chip for Image Processing Applications.	Lars Braun, Michael Hbner, Jrgen Becker, Thomas Perschke, Volker Schatz, Stefan Bach
2007	A floating-point Extended Kalman Filter implementation for autonomous mobile robots.	Vanderlei Bonato, Eduardo Marques, George A. Constantinides
2007	Hardware/Software Process Migration and RTL Simulation.	Aric D. Blumer, Cameron D. Patterson
2007	Formal Modeling of Process Migration.	Aric D. Blumer, Henning S. Mortveit, Cameron D. Patterson
2007	Pre-route Interconnect Capacitance and Power Estimation in FPGAs.	Shilpa Bhoj, Dinesh Bhatia
2007	The Intel Geneseo Project.	Ajay V. Bhatt
2007	A Design Flow to Map Parallel Applications onto FPGAs.	Sbastien Le Beux, Philippe Marquet, Jean-Luc Dekeyser
2007	C++ based design flow for reconfigurable image processing systems.	Rob Beun, Irek Karkowski, Maarten Ditzel
2007	HARTES Toolchain Early Evaluation: Profiling, Compilation and HDL Generation.	Koen Bertels, Georgi Kuzmanov, Elena Moscu Panainte, Georgi Gaydadjiev, Yana Yankova, Vlad Mihai Sima, Kamana Sigdel, Roel Meeuws, Stamatis Vassiliadis
2007	Multiplexer-based routing fabric for reconfigurable logic.	Martijn T. Bennebroek, Alexander Danilin
2007	Wires On Demand: Run-Time Communication Synthesis for Reconfigurable Computing.	Peter M. Athanas, John W. Bowen, Timothy Dunham, Cameron D. Patterson, J. Rice, Matthew Shelburne, Jorge Surs, Mark B. Bucciero, Jonathan Graf
2007	Supporting High Level Language Semantics Within Hardware Resident Threads.	Erik K. Anderson, Wesley Peck, Jim Stevens, Jason Agron, Fabrice Baijot, Seth Warn, David Andrews

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