| 2006 | On Feasibility of FPGA Bitstream Compression During Placement and Routing. | Piotr Stepien, Milan Vasilko |
| 2006 | Integrating the Electronics of the Control-Loops of the JPL/Boeing Gyroscope Within an Evolvable Hardware Architecture. | Evangelos F. Stefatos, Tughrul Arslan, Didier Keymeulen, Ian Ferguson |
| 2006 | FPGA Implementations of the DES and Triple-DES Masked Against Power Analysis Attacks. | Franois-Xavier Standaert, Gal Rouvroy, Jean-Jacques Quisquater |
| 2006 | High Speed High Fidelity Infrared Scene Simulation Using Reconfigurable Computing. | Vinay Sriram, David Kearney |
| 2006 | FPGA Implementation of High-Performance PHM / DPHM Schedulers. | Enrique Soto, Elena Lago, Juan J. Rodrguez-Andina |
| 2006 | FPGA Implementation of a Change-Driven Image Processing Architecture for Optical Flow Computation. | Julio C. Sosa, Roco Gmez-Fabela, Jose Antonio Boluda, Fernando Pardo |
| 2006 | Improving Usability of FPGA-Based Reconfigurable Computers Through Operating System Support. | Hayden Kwok-Hay So, Robert W. Brodersen |
| 2006 | A Novel Heuristic and Provable Bounds for Reconfigurable Architecture Design. | Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung |
| 2006 | Wire Segment Length and Switch Box Co-Optimization for FPGA Architectures. | Kostas Siozios, Dimitrios Soudris |
| 2006 | Multi-layer Floorplanning on a Sequence of Reconfigurable Designs. | Love Singhal, Elaheh Bozorgzadeh |
| 2006 | An FPGA Implementation of Pattern-Selective Pyramidal Image Fusion. | Oliver Sims, James Irvine |
| 2006 | A System Design Methodology for Reducing System Integration Time and Facilitating Modular Design Verification. | Lesley Shannon, Blair Fort, Samir Parikh, Arun Patel, Manuel Saldaa, Paul Chow |
| 2006 | Multi2 Router: A Novel Multi Local Port Router Architecture with Broadcast Facility for FPGA-Based Networks-on-Chip. | Balasubramanian Sethuraman, Ranga Vemuri |
| 2006 | Novel Methodologies for Performance & Power Efficient Reconfigurable Networks-on-Chip. | Balasubramanian Sethuraman |
| 2006 | FPGA Vendor Agnostic True Random Number Generator. | Dries Schellekens, Bart Preneel, Ingrid Verbauwhede |
| 2006 | OSSS+R: Modelling and Simulating Self-Reconfigurable Systems. | Andreas Schallenberg, Wolfgang Nebel, Frank Oppenheimer |
| 2006 | A High Speed, Low Memory FPGA Based LDPC Decoder Architecture for Quasi-Cyclic LDPC Codes. | Paul Saunders, Anthony D. Fagan |
| 2006 | Partial Dynamic Reconfiguration: The Caronte Approach. A New Degree of Freedom in the HW/SW Codesign. | Marco D. Santambrogio, Donatella Sciuto |
| 2006 | TMD-MPI: An MPI Implementation for Multiple Processors Across Multiple FPGAs. | Manuel Saldaa, Paul Chow |
| 2006 | An FPGA Implementation of K-Means Clustering for Color Images Based on Kd-Tree. | Takashi Saegusa, Tsutomu Maruyama |
| 2006 | Adaptive Optics Real-Time Control Using FPGA. | Luis F. Rodrguez-Ramos, Angel Alonso, Fernando Gago, Jose V. Gigante, Guillermo Herrera, Teodora Viera |
| 2006 | Shift-Or Circuit for Efficient Network Intrusion Detection Pattern Matching. | Huang-Chun Roan, Wen-Jyi Hwang, Chia-Tien Dan Lo |
| 2006 | Configuration Scheduling for Conditional Branch Execution Onto Multi-Context Reconfigurable Architectures. | Fredy Rivera, Marcos Snchez-lez, Milagros Fernndez, Romn Hermida, Nader Bagherzadeh |
| 2006 | A Scalable Network ASIP Enabling Flow Awareness in Ethernet Access. | Koen Van Renterghem, Dieter Verhulst, S. Verschuere, Pieter Demuytere, Jan Vandewege, Xing-Zhi Qiu |
| 2006 | A Dual Cache for Performance and Energy Aware Reconfigurable HW. | Elena Perez Ramo, Javier Resano |