| 2005 | Optimization of Start-Up Time and Quiescent Power Consumption of FPGAs. | Artur Schiefer, Udo Kebschull |
| 2005 | Programmable Numerical Function Generators: Architectures and Synthesis Method. | Tsutomu Sasao, Shinobu Nagayama, Jon T. Butler |
| 2005 | Cluster Architecture for Reconfigurable Signal Processing Engine for Wireless Communication. | Miyoshi Saito, Hisanori Fujisawa, Nobuo Ujiie, Hideki Yoshizawa |
| 2005 | FPGA's Middleware for Software Defined Radio Applications. | Xavier Revs, Vuk Marojevic, Ramon Ferrs, Antoni Gelonch |
| 2005 | An FPGA-based Soft Multiprocessor System for IPv4 Packet Forwarding. | Kaushik Ravindran, Nadathur Satish, Yujia Jin, Kurt Keutzer |
| 2005 | Coping With Uncertainty in FPGA Architecture Design. | Boris Ratchev, Mike Hutton, David Mendel |
| 2005 | An Efficient Approach to Hide the Run-Time Reconfiguration from SW Applications. | Yang Qu, Juha-Pekka Soininen, Jari Nurmi |
| 2005 | GALS systems prototyping using multiclock FPGAs and asynchronous network-on-chips. | Jerome Quartana, Salim Renane, Arnaud Baixas, Laurent Fesquet, Marc Renaudin |
| 2005 | An Emulation Model for Sequential ATPG-Based Bounded Model Checking. | Qiang Qiang, Daniel G. Saab, Jacob A. Abraham |
| 2005 | FPGA-Accelerated Reconstruction of Gene Regulatory Networks. | Iosifina Pournara, Christos-Savvas Bouganis, George A. Constantinides |
| 2005 | Performance Tuning of Iterative Algorithms in Signal Processing. | Zdenek Pohl, Premysl Sucha, Jiri Kadlec, Zdenek Hanzlek |
| 2005 | Design and FPGA Implementation of an Embedded Real-Time Biologically Plausible Spiking Neural Network Processor. | Martin J. Pearson, Chris Melhuish, Anthony G. Pipe, Mokhtar Nibouche, Ian Gilhespy, Kevin N. Gurney, Benjamin Mitchinson |
| 2005 | MechanoProcessor: Modelling the Rodent Whisker Sensory System using FPGA. | Martin J. Pearson |
| 2005 | FPGA Finite-Difference Time-Domain solver for thermal simulation. | Fernando Pardo, Paula Lpez, Diego Cabello, Marco Balsi |
| 2005 | Hashing + Memory = Low Cost, Exact Pattern Matching. | Giorgos Papadopoulos, Dionisios N. Pnevmatikatos |
| 2005 | On-Chip Communication Topology Synthesis for a Shared Memory Architecture. | Sujan Pandey, Manfred Glesner, Max Mhlhuser |
| 2005 | A Framework for ODE-Based Multimodel Biochemical Simulations on an FPGA. | Yasunori Osana, Yow Iwaoka, Tomonori Fukushima, Masato Yoshimi, Akira Funahashi, Noriko Hiroi, Yuichiro Shibata, Naoki Iwanaga, Hiroaki Kitano, Hideharu Amano |
| 2005 | Evaluation of Ray Casting on Processor-Like Reconfigurable Architectures. | Tobias Oppold, Thomas Schweizer, Tommy Kuhn, Wolfgang Rosenstiel, Urs Kanus, Wolfgang Straer |
| 2005 | Hardware Emulation of a Network on Chip Architecture based on a Clockwork Routed Manhattan Street Network. | Kurian Oommen, David Harle |
| 2005 | Performance and Energy Analysis of Task-Level Graph Transformation Techniques for Dynamically Reconfigurable Architectures. | Juanjo Noguera, Rosa M. Badia |
| 2005 | Real-time Generation of Three-Dimensional Motion Fields. | Hiroaki Niitsuma, Tsutomu Maruyama |
| 2005 | Real-Time Feature Extraction for High Speed Networks. | David Nguyen, Gokhan Memik, Seda Ogrenci Memik, Alok N. Choudhary |
| 2005 | Reconfigurable Architectures for Real-Time Network Anomaly Detection. | David Nguyen |
| 2005 | Figaro - An Automatic Tool Flow for Designs with Dynamic Reconfiguration. | Kelly Nasi, Martin Danek, Theodoros Karoubalis, Zdenek Pohl |
| 2005 | Using DSP Blocks For ROM Replacement: A Novel Synthesis Flow. | Gareth W. Morris, George A. Constantinides, Peter Y. K. Cheung |