| 2010 | Process variation aware performance modeling and dynamic power management for multi-core systems. | Siddharth Garg, Diana Marculescu, Sebastian Herbert |
| 2010 | Efficient state space exploration: Interleaving stateless and state-based model checking. | Malay K. Ganai, Chao Wang, Weihong Li |
| 2010 | Fast thermal analysis on GPU for 3D-ICs with integrated microchannel cooling. | Zhuo Feng, Peng Li |
| 2010 | Redundant-wires-aware ECO timing and mask cost optimization. | Shao-Yun Fang, Tzuo-Fan Chien, Yao-Wen Chang |
| 2010 | Characterization of the worst-case current waveform excitations in general RLC-model power grid analysis. | Nestoras E. Evmorfopoulos, Maria-Aikaterini Rammou, George I. Stamoulis, John Moondanos |
| 2010 | Timing yield optimization via discrete gate sizing using globally-informed delay PDFs. | Shantanu Dutt, Huan Ren |
| 2010 | Reliability, thermal, and power modeling and optimization. | Robert P. Dick |
| 2010 | Phase equations for quasi-periodic oscillators. | Alper Demir, Chenjie Gu, Jaijeet S. Roychowdhury |
| 2010 | Credit Borrow and Repay: Sharing DRAM with minimum latency and bandwidth guarantees. | Zefu Dai, Mark Jarvin, Jianwen Zhu |
| 2010 | Design-hierarchy aware mixed-size placement for routability optimization. | Yi-Lin Chuang, Gi-Joon Nam, Charles J. Alpert, Yao-Wen Chang, Jarrod A. Roy, Natarajan Viswanathan |
| 2010 | Formal deadlock checking on high-level SystemC designs. | Chun-Nan Chou, Chang-Hong Hsu, Yueh-Tung Chao, Chung-Yang Huang |
| 2010 | Bi-decomposition of large Boolean functions using blocking edge graphs. | Mihir R. Choudhury, Kartik Mohanram |
| 2010 | Novel binary linear programming for high performance clock mesh synthesis. | Minsik Cho, David Z. Pan, Ruchir Puri |
| 2010 | Design method and test structure to characterize and repair TSV defect induced signal degradation in 3D system. | Minki Cho, Chang Liu, Dae Hyun Kim, Sung Kyu Lim, Saibal Mukhopadhyay |
| 2010 | Memory access aware on-line voltage control for performance and energy optimization. | Xi Chen, Chi Xu, Robert P. Dick |
| 2010 | Cost-effective integration of three-dimensional (3D) ICs emphasizing testing cost analysis. | Yibo Chen, Dimin Niu, Yuan Xie, Krishnendu Chakrabarty |
| 2010 | MVP: Capture-power reduction with minimum-violations partitioning for delay testing. | Zhen Chen, Krishnendu Chakrabarty, Dong Xiang |
| 2010 | Native-conflict-aware wire perturbation for double patterning technology. | Szu-Yu Chen, Yao-Wen Chang |
| 2010 | Scheduling of synchronous data flow models on scratchpad memory based embedded processors. | Weijia Che, Karam S. Chatha |
| 2010 | Mathematical yield estimation for two-dimensional-redundancy memory arrays. | Mango Chia-Tso Chao, Ching-Yu Chin, Chen-Wei Lin |
| 2010 | Design dependent process monitoring for back-end manufacturing cost reduction. | Tuck-Boon Chan, Aashish Pant, Lerong Cheng, Puneet Gupta |
| 2010 | GLADE: A modern global router considering layer directives. | Yen-Jung Chang, Tsung-Hsien Lee, Ting-Chi Wang |
| 2010 | Post-placement power optimization with multi-bit flip-flops. | Yao-Tsung Chang, Chih-Cheng Hsu, Mark Po-Hung Lin, Yu-Wen Tsai, Sheng-Fong Chen |
| 2010 | Online selection of effective functional test programs based on novelty detection. | Po-Hsien Chang, Dragoljub Gagi Drmanac, Li-C. Wang |
| 2010 | Flexible interpolation with local proof transformations. | Roberto Bruttomesso, Simone Rollini, Natasha Sharygina, Aliaksei Tsitovich |