| 2009 | A method for calculating hard QoS guarantees for Networks-on-Chip. | Dara Rahmati, Srinivasan Murali, Luca Benini, Federico Angiolini, Giovanni De Micheli, Hamid Sarbazi-Azad |
| 2009 | The synthesis of combinational logic to generate probabilities. | Weikang Qian, Marc D. Riedel, Kia Bazargan, David J. Lilja |
| 2009 | From 2D to 3D NoCs: A case study on worst-case communication performance. | Yue Qian, Zhonghai Lu, Wenhua Dou |
| 2009 | On soft error rate analysis of scaled CMOS designs - A statistical perspective. | Huan-Kai Peng, Charles H.-P. Wen, Jayanta Bhadra |
| 2009 | A variation-aware preferential design approach for memory based reconfigurable computing. | Somnath Paul, Saibal Mukhopadhyay, Swarup Bhunia |
| 2009 | A circuit-software co-design approach for improving EDP in reconfigurable frameworks. | Somnath Paul, Subho Chatterjee, Saibal Mukhopadhyay, Swarup Bhunia |
| 2009 | Timing Arc based logic analysis for false noise reduction. | Murthy Palla, Jens Bargfrede, Stephan Eggersgl, Walter Anheier, Rolf Drechsler |
| 2009 | Exact route matching algorithms for analog and mixed signal integrated circuits. | Muhammet Mustafa Ozdal, Renato Fernandes Hentschke |
| 2009 | PSTA-based branch and bound approach to the silicon speedpath isolation problem. | Sari Onaissi, Khaled R. Heloue, Farid N. Najm |
| 2009 | SAT-based protein design. | Noah Ollikainen, Ellen Sentovich, Carlos Coelho, Andreas Kuehlmann, Tanja Kortemme |
| 2009 | A performance analytical model for Network-on-Chip with constant service time routers. | Nikita Nikitin, Jordi Cortadella |
| 2009 | Genetic design automation. | Chris J. Myers, Nathan A. Barker, Hiroyuki Kuwahara, Kevin R. Jones, Curtis Madsen, Nam-Phuong D. Nguyen |
| 2009 | Global routing revisited. | Michael D. Moffitt |
| 2009 | Thermal modeling for 3D-ICs with integrated microchannel cooling. | Hitoshi Mizunuma, Chia-Lin Yang, Yi-Chang Lu |
| 2009 | A novel post-ATPG IR-drop reduction scheme for at-speed scan testing in broadcast-scan-based test compression environment. | Kohei Miyase, Yuta Yamato, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Xiaoqing Wen, Seiji Kajihara |
| 2009 | Battery allocation for wireless sensor network lifetime maximization under cost constraints. | Hengyu Long, Yongpan Liu, Yiqun Wang, Robert P. Dick, Huazhong Yang |
| 2009 | Obstacle-avoiding rectilinear Steiner tree construction based on Steiner point selection. | Chih-Hung Liu, Shih-Yi Yuan, Sy-Yen Kuo, Jung-Hung Weng |
| 2009 | Virtual probe: A statistically optimal framework for minimum-cost silicon characterization of nanoscale integrated circuits. | Xin Li, Rob A. Rutenbar, R. D. (Shawn) Blanton |
| 2009 | Generation of optimal obstacle-avoiding rectilinear Steiner minimum tree. | Liang Li, Zaichen Qian, Evangeline F. Y. Young |
| 2009 | Pad assignment for die-stacking System-in-Package design. | Yu-Chen Lin, Wai-Kei Mak, Chris Chu, Ting-Chi Wang |
| 2009 | MOLES: Malicious off-chip leakage enabled by side-channels. | Lang Lin, Wayne P. Burleson, Christof Paar |
| 2009 | Operating system scheduling for efficient online self-test in robust systems. | Yanjing Li, Onur Mutlu, Subhasish Mitra |
| 2009 | Timing model extraction for sequential circuits considering process variations. | Bing Li, Ning Chen, Ulf Schlichtmann |
| 2009 | Retiming and time borrowing: Optimizing high-performance pulsed-latch-based circuits. | Seonggwan Lee, Seungwhun Paik, Youngsoo Shin |
| 2009 | An efficient pre-assignment routing algorithm for flip-chip designs. | Po-Wei Lee, Chung-Wei Lin, Yao-Wen Chang, Chin-Fang Shen, Wei-Chih Tseng |