| 2005 | FastSies: a fast stochastic integral equation solver for modeling the rough surface effect. | Zhenhai Zhu, Jacob K. White |
| 2005 | Improving the efficiency of static timing analysis with false paths. | Shuo Zhou, Bo Yao, Hongyu Chen, Yi Zhu, Chung-Kuan Cheng, Michael D. Hutton, Truman Collins, Sridhar Srinivasan, Nan-Chi Chou, Peter Suaris |
| 2005 | Fast algorithms for IR drop analysis in large power grid. | Yu Zhong, Martin D. F. Wong |
| 2005 | Statistical critical path analysis considering correlations. | Yaping Zhan, Andrzej J. Strojwas, Mahesh Sharma, David Newmark |
| 2005 | A high efficiency full-chip thermal simulation algorithm. | Yong Zhan, Sachin S. Sapatnekar |
| 2005 | Scalable compositional minimization via static analysis. | Fadi A. Zaraket, Jason Baumgartner, Adnan Aziz |
| 2005 | Timing-aware power noise reduction in layout. | Chao-Yang Yeh, Malgorzata Marek-Sadowska |
| 2005 | Noise margin analysis for dynamic logic circuits. | Suwen Yang, Mark R. Greenstreet |
| 2005 | DiCER: distributed and cost-effective redundancy for variation tolerance. | Di Wu, Ganesh Venkataraman, Jiang Hu, Quiyang Li, Rabi N. Mahapatra |
| 2005 | Post-placement voltage island generation under performance requirement. | Huaizhi Wu, I-Min Liu, Martin D. F. Wong, Yusu Wang |
| 2005 | FPGA device and architecture evaluation considering process variations. | Ho-Yan Wong, Lerong Cheng, Yan Lin, Lei He |
| 2005 | Fast balanced stochastic truncation via a quadratic extension of the alternating direction implicit iteration. | Ngai Wong, Venkataramanan Balakrishnan |
| 2005 | System-level power and thermal modeling and analysis by orthogonal polynomial based response surface approach (OPRS). | Janet Meiling Wang, Bharat Srinivas, Dongsheng Ma, Charlie Chung-Ping Chen, Jun Li |
| 2005 | Mixed-size placement via line search. | Kristofer Vorwerk, Andrew A. Kennings |
| 2005 | Weighted control scheduling. | Aravind Vijayakumar, Forrest Brewer |
| 2005 | Practical techniques to reduce skew and its variations in buffered clock networks. | Ganesh Venkataraman, Nikhil Jayakumar, Jiang Hu, Peng Li, Sunil P. Khatri, Anand Rajaram, Patrick McGuinness, Charles J. Alpert |
| 2005 | A more reliable reduction algorithm for behavioral model extraction. | Dmitry Vasilyev, Jacob K. White |
| 2005 | Worst-case analysis to obtain stable read/write DC margin of high density 6T-SRAM-array with local Vth variability. | Yasumasa Tsukamoto, Koji Nii, Susumu Imaoka, Yuji Oda, Shigeki Ohbayashi, Tomoaki Yoshizawa, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara |
| 2005 | Statistical timing analysis driven post-silicon-tunable clock-tree synthesis. | Jeng-Liang Tsai, Lizheng Zhang |
| 2005 | Physics-based compact modeling for nonclassical CMOS. | Vishal P. Trivedi, Jerry G. Fossum, Leo Mathew, Murshed M. Chowdhury, Weimin Zhang, Glenn O. Workman, Bich-Yen Nguyen |
| 2005 | The circuit design of the synergistic processor element of a CELL processor. | Osamu Takahashi, Russ Cook, Scott R. Cottier, Sang H. Dhong, Brian K. Flachs, Koji Hirairi, Atsushi Kawasumi, Hiroaki Murakami, Hiromi Noro, Hwa-Joon Oh, S. Onish, Juergen Pille, Joel Silberman |
| 2005 | A mapping algorithm for defect-tolerance of reconfigurable nano-architectures. | Mehdi Baradaran Tahoori |
| 2005 | Total power-optimal pipelining and parallel processing under process variations in nanometer technology. | Peter Suaris, Taeho Kgil, Keith A. Bowman, Vivek De, Trevor N. Mudge |
| 2005 | New decompilation techniques for binary-level co-processor generation. | Greg Stiff, Frank Vahid |
| 2005 | Digital RF processor (DRP™) for cellular phones. | Robert Bogdan Staszewski, Khurram Muhammad, Dirk Leipold |