| 2005 | Performance analysis of carbon nanotube interconnects for VLSI applications. | Navin Srivastava, Kaustav Banerjee |
| 2005 | An automated technique for topology and route generation of application specific on-chip interconnection networks. | Krishnan Srinivasan, Karam S. Chatha, Goran Konjevod |
| 2005 | A unified framework for statistical timing analysis with coupling and multiple input switching. | Debjit Sinha, Hai Zhou |
| 2005 | Statistical gate sizing for timing yield optimization. | Debjit Sinha, Narendra V. Shenoy, Hai Zhou |
| 2005 | Statistical technology mapping for parametric yield. | Ashish Kumar Singh, Murari Mani, Michael Orshansky |
| 2005 | Fast timing closure by interconnect criticality driven delay relaxation. | Love Singhal, Elaheh Bozorgzadeh |
| 2005 | Memory access optimization of dynamic binary translation for reconfigurable architectures. | Montek Singh |
| 2005 | Equivalence verification of polynomial datapaths with fixed-size bit-vectors using finite ring algebra. | Namrata Shekhar, Priyank Kalla, Florian Enescu, Sivaram Gopalakrishnan |
| 2005 | Expanding the frequency range of AWE via time shifting. | Ahmed M. Shebaita, Chirayu S. Amin, Florentin Dartu, Yehea I. Ismail |
| 2005 | Discrete Vt assignment and gate sizing using a self-snapping continuous formulation. | Saumil Shah, Ashish Srivastava, Dushyant Sharma, Dennis Sylvester, David T. Blaauw, Vladimir Zolotov |
| 2005 | Optimal integration of inter-task and intra-task dynamic voltage scaling techniques for hard real-time applications. | Jaewon Seo, Taewhan Kim, Nikil D. Dutt |
| 2005 | Test planning for the effective utilization of port-scalable testers for heterogeneous core-based SOCs. | Anuja Sehgal, Krishnendu Chakrabarty |
| 2005 | Power-aware microsensor design. | Brian Schott, Michael Bajura |
| 2005 | Deadlock-free routing and component placement for irregular mesh-based networks-on-chip. | Martin K. F. Schafer, Thomas Hollstein, Heiko Zimmer, Manfred Glesner |
| 2005 | Performance-driven read-after-write dependencies softening in high-level synthesis. | Rafael Ruiz-Sautua, Mara C. Molina, Jose Manuel Mendias, Romn Hermida |
| 2005 | Double-gate SOI devices for low-power and high-performance applications. | Kaushik Roy, Hamid Mahmoodi-Meimand, Saibal Mukhopadhyay, Hari Ananthan, Aditya Bansal, Tamer Cakici |
| 2005 | SAT based solutions for consistency problems in formal property specifications for open systems. | Suchismita Roy, Sayantan Das, Prasenjit Basu, Pallab Dasgupta, Partha Pratim Chakrabarti |
| 2005 | ConvexFit: an optimal minimum-error convex fitting and smoothing algorithm with application to gate-sizing. | Sanghamitra Roy, Weijen Chen |
| 2005 | Thermal simulation techniques for nanoscale transistors. | Jeremy A. Rowlette, Eric Pop, Sanjiv Sinha, Mathew Panzer, Kenneth E. Goodson |
| 2005 | Design of DNA origami. | Paul W. K. Rothemund |
| 2005 | Cellular wave computers and CNN technology - a SoC architecture with xK processors and sensor arrays. | Tams Roska |
| 2005 | Hardware synthesis from guarded atomic actions with performance specifications. | Daniel L. Rosenband |
| 2005 | System level verification of digital signal processing applications based on the polynomial abstraction technique. | Tarvo Raudvere, Ashish Kumar Singh, Ingo Sander, Axel Jantsch |
| 2005 | Battery optimization vs energy optimization: which to choose and when? | Ravishankar Rao, Sarma B. K. Vrudhula |
| 2005 | Via-configurable routing architectures and fast design mappability estimation for regular fabrics. | Yajun Ran, Malgorzata Marek-Sadowska |