| 2001 | Integral Design Representations for Embedded Systems. | Lothar Thiele |
| 2001 | A Simulation-Based Method for the Verification of Shared Memory in Multiprocessor Systems. | Scott A. Taylor, Carl Ramey, Craig Barner, David Asher |
| 2001 | A New Algorithm for Routing Tree Construction with Buffer Insertion and Wire Sizing under Obstacle Constraints. | Xiaoping Tang, Ruiqi Tian, Hua Xiang, D. F. Wong |
| 2001 | Hybrid Structured Clock Network Construction. | Haihua Su, Sachin S. Sapatnekar |
| 2001 | Crosstalk Fault Detection by Dynamic Idd. | Xiaoyun Sun, Seonki Kim, Bapiraju Vinnakota |
| 2001 | Verification of Integer Multipliers on the Arithmetic Bit Level. | Dominik Stoffel, Wolfgang Kunz |
| 2001 | Sequential SPFDs. | Subarnarekha Sinha, Andreas Kuehlmann, Robert K. Brayton |
| 2001 | Energy Efficient Real-Time Scheduling. | Amit Sinha, Anantha P. Chandrakasan |
| 2001 | Interconnect Resource-Aware Placement for Hierarchical FPGAs. | Amit Singh, Ganapathy Parthasarathy, Malgorzata Marek-Sadowska |
| 2001 | Recursive Bipartitioning of BDDs for Performance Driven Synthesis of Pass Transistor Logic Circuits. | Rupesh S. Shelar, Sachin S. Sapatnekar |
| 2001 | Accurate CMOS Bridge Fault Modeling with Neural Network-Based VHDL Saboteurs. | Donald B. Shaw, Dhamin Al-Khalili, Cme Rozon |
| 2001 | Automatic Hierarchical Design: Fantasy or Reality? (Panel). | Rob A. Rutenbar, Olivier Coudert, Patrick Groeneveld, Jrgen Koehl, Scott Peterson, Vivek Raghavan, Naresh Soni |
| 2001 | Power-Delay Modeling of Dynamic CMOS Gates for Circuit Optimization. | Jos Luis Rossell, Jaume Segura |
| 2001 | A Trajectory Piecewise-Linear Approach to Model Order Reduction and Fast Simulation of Nonlinear Circuits and Micromachined Devices. | Michal Rewienski, Jacob White |
| 2001 | An Analytical High-Level Battery Model for Use in Energy Management of Portable Electronic Systems. | Daler N. Rakhmatov, Sarma B. K. Vrudhula |
| 2001 | Transient Power Management Through High Level Synthesis. | Vijay Raghunathan, Srivaths Ravi, Anand Raghunathan, Ganesh Lakshminarayana |
| 2001 | What is the Limit of Energy Saving by Dynamic Voltage Scaling? | Gang Qu |
| 2001 | Simulation Approaches for Strongly Coupled Interconnect Systems. | Joel R. Phillips, Lus Miguel Silveira |
| 2001 | Symbolic Algebra and Timing Driven Data-flow Synthesis. | Armita Peymandoust, Giovanni De Micheli |
| 2001 | I-CoPES: Fast Instruction Code Placement for Embedded Systems to Improve Performance and Energy Efficiency. | Sri Parameswaran, Jrg Henkel |
| 2001 | Placement Driven Retiming with a Coupled Edge Timing Model. | Ingmar Neumann, Wolfgang Kunz |
| 2001 | A Force-Directed Maze Router. | Fan Mo, Abdallah Tabbara, Robert K. Brayton |
| 2001 | On the Optimization Power of Redundancy Addition and Removal Techniques for Sequential Circuits. | Enrique San Milln, Luis Entrena, Jos Alberto Espejo |
| 2001 | NetBench: A Benchmarking Suite for Network Processors. | Gokhan Memik, William H. Mangione-Smith, Wendong Hu |
| 2001 | A Super-Scheduler for Embedded Reconfigurable Systems. | Seda Ogrenci Memik, Elaheh Bozorgzadeh, Ryan Kastner, Majid Sarrafzadeh |