| 2000 | Slope Propagation in Static Timing Analysis. | David T. Blaauw, Vladimir Zolotov, Savithri Sundareswaran, Chanhee Oh, Rajendran Panda |
| 2000 | Why Doesn't EDA Get Enough Respect? | Andreas von Bechtolsheim, Joe Costello, Aart de Gues, Patrick Scaglia, Jennifer Smith |
| 2000 | Hierarchical Interconnect Circuit Models. | Michael W. Beattie, Satrajit Gupta, Lawrence T. Pileggi |
| 2000 | Modeling Non-Slicing Floorplans with Binary Trees. | Florin Balasa |
| 2000 | Simulation and Optimization of the Power Distribution Network in VLSI Circuits. | Geng Bai, Sudhakar Bobba, Ibrahim N. Hajj |
| 1999 | Timing-driven partitioning for two-phase domino and mixed static/domino implementations. | Min Zhao, Sachin S. Sapatnekar |
| 1999 | Partial BIST insertion to eliminate data correlation. | Qiushuang Zhang, Ian G. Harris |
| 1999 | Modeling design constraints and biasing in simulation using BDDs. | Jun Yuan, Kurt Shultz, Carl Pixley, Hillel Miller, Adnan Aziz |
| 1999 | RLC interconnect delay estimation via moments of amplitude and phase response. | Xiaodong Yang, Walter H. Ku, Chung-Kuan Cheng |
| 1999 | Implicit enumeration of strongly connected components. | Aiguo Xie, Peter A. Beerel |
| 1999 | Path toward future CAD environments for MEMS (tutorial abstract). | Jacob K. White, Gary K. Fedder, Tamal Mukherjee |
| 1999 | Advances in transistor timing, simulation, and optimization (tutorial abstract). | Jacob White, Jacob Avidan, Ibrahim Abe M. Elfadel, D. F. Wong |
| 1999 | A wide frequency range surface integral formulation for 3-D RLC extraction. | Junfeng Wang, Johannes Tausch, Jacob K. White |
| 1999 | The Chebyshev expansion based passive model for distributed interconnect networks. | Janet Meiling Wang, Ernest S. Kuh, Qingjian Yu |
| 1999 | Formulation of static circuit optimization with reduced size, degeneracy and redundancy by timing graph manipulation. | Chandramouli Visweswariah, Andrew R. Conn |
| 1999 | Deep submicron defect detection with the energy consumption ratio. | Bapiraju Vinnakota |
| 1999 | Optimal allocation of carry-save-adders in arithmetic optimization. | Junhyung Um, Taewhan Kim, C. L. Liu |
| 1999 | FunState - an internal design representation for codesign. | Lothar Thiele, Karsten Strehl, Dirk Ziegenbein, Rolf Ernst, Jrgen Teich |
| 1999 | Performance optimization using separator sets. | Yutaka Tamiya |
| 1999 | SAT based ATPG using fast justification and propagation in the implication graph. | Paul Tafertshofer, Andreas Ganz |
| 1999 | Marsh: min-area retiming with setup and hold constraints. | Vijay Sundararajan, Sachin S. Sapatnekar, Keshab K. Parhi |
| 1999 | Validation and test generation for oscillatory noise in VLSI interconnects. | Arani Sinha, Sandeep K. Gupta, Melvin A. Breuer |
| 1999 | Body-voltage estimation in digital PD-SOI circuits and its application to static timing analysis. | Kenneth L. Shepard, Dae-Jin Kim |
| 1999 | TICER: realizable reduction of extracted RC circuits. | Bernard N. Sheehan |
| 1999 | AKORD: transistor level and mixed transistor/gate level placement tool for digital data paths. | Tatjana Serdar, Carl Sechen |