| 1998 | Robust latch mapping for combinational equivalence checking. | Jerry R. Burch, Vigyan Singhal |
| 1998 | Interface synthesis: a vertical slice from digital logic to software components. | Gaetano Borriello, Luciano Lavagno, Ross B. Ortega |
| 1998 | Dynamic fault collapsing and diagnostic test pattern generation for sequential circuits. | Vamsi Boppana, W. Kent Fuchs |
| 1998 | Static compaction using overlapped restoration and segment pruning. | Surendra Bommu, Srimat T. Chakradhar, Kiran B. Doreswamy |
| 1998 | Node sampling: a robust RTL power modeling approach. | Alessandro Bogliolo, Luca Benini |
| 1998 | Dynamic power management of electronic systems. | Luca Benini, Alessandro Bogliolo, Giovanni De Micheli |
| 1998 | Gate-size selection for standard cell libraries. | Frederik Beeftink, Prabhakar Kudva, David S. Kung, Leon Stok |
| 1998 | Verification of RTL generated from scheduled behavior in a high-level synthesis flow. | Pranav Ashar, Subhrajit Bhattacharya, Anand Raghunathan, Akira Mukaiyama |
| 1998 | How will CAD handle billion-transistor systems? (panel). | Robert C. Aitken, Jason Cong, Randy Harr, Kenneth L. Shepard, Wayne H. Wolf |
| 1997 | Hybrid spectral/iterative partitioning. | Jason Y. Zien, Pak K. Chan, Martine D. F. Schlag |
| 1997 | An exact gate decomposition algorithm for low-power technology mapping. | Hai Zhou, D. F. Wong |
| 1997 | Test and diagnosis of fault logic blocks in FPGAs. | Sying-Jyan Wang, Tsi-Ming Tsai |
| 1997 | COSMOS: a continuous optimization approach for maximum power estimation of CMOS circuits. | Chuan-Yu Wang, Kaushik Roy |
| 1997 | Generalized matching from theory to application. | Patrick Vuillod, Luca Benini, Giovanni De Micheli |
| 1997 | Optimization techniques for high-performance digital circuits. | Chandramouli Visweswariah |
| 1997 | A deductive technique for diagnosis of bridging faults. | Srikanth Venkataraman, W. Kent Fuchs |
| 1997 | Test generation for comprehensive testing of linear analog circuits using transient response sampling. | Pramodchandran N. Variyam, Abhijit Chatterjee |
| 1997 | Optimal wire and transistor sizing for circuits with non-tree topology. | Lieven Vandenberghe, Stephen P. Boyd, Abbas El Gamal |
| 1997 | Test generation for primitive path delay faults in combinational circuits. | Ramesh C. Tekumalla, Premachandran R. Menon |
| 1997 | Clock-tree routing realizing a clock-schedule for semi-synchronous circuits. | Atsushi Takahashi, Kazunori Inoue, Yoji Kajitani |
| 1997 | A SAT-based implication engine for efficient ATPG, equivalence checking, and optimization of netlists. | Paul Tafertshofer, Andreas Ganz, Manfred Henftling |
| 1997 | Fast field solver-programs for thermal and electrostatic analysis of microsystem elements. | Vladimr Szkely, Mrta Rencz |
| 1997 | Post-route optimization for improved yield using a rubber-band wiring model. | Jeffrey Z. Su, Wayne Wei-Ming Dai |
| 1997 | Record & play: a structural fixed point iteration for sequential circuit verification. | Dominik Stoffel, Wolfgang Kunz |
| 1997 | EDA and the network. | Mark D. Spiller, A. Richard Newton |