| 1998 | Optimal 2-D cell layout with integrated transistor folding. | Avaneendra Gupta, John P. Hayes |
| 1998 | Determination of worst-case aggressor alignment for delay calculation. | Paul D. Gross, Ravishankar Arunachalam, Karthik Rajagopal, Lawrence T. Pileggi |
| 1998 | Verification by approximate forward and backward reachability. | Shankar G. Govindaraju, David L. Dill |
| 1998 | Simulation of high-Q oscillators. | Mark M. Gourary, Sergey L. Ulyanov, Michael M. Zharov, Sergey G. Rusakov |
| 1998 | Wireplanning in logic synthesis. | Wilsin Gosti, Amit Narayan, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
| 1998 | Shaping a VLSI wire to minimize delay using transmission line model. | Youxin Gao, D. F. Wong |
| 1998 | Symbolic algorithms for layout-oriented synthesis of pass transistor logic circuits. | Fabrizio Ferrandi, Alberto Macii, Enrico Macii, Massimo Poncino, Riccardo Scarsi, Fabio Somenzi |
| 1998 | CORDS: hardware-software co-synthesis of reconfigurable real-time distributed embedded systems. | Robert P. Dick, Niraj K. Jha |
| 1998 | High-level design validation and test. | Sujit Dey, Jacob A. Abraham, Yervant Zorian |
| 1998 | Phase noise in oscillators: DAEs and colored noise sources. | Alper Demir |
| 1998 | Efficient analog circuit synthesis with simultaneous yield and robustness optimization. | Geert Debyser, Georges G. E. Gielen |
| 1998 | Lazy transition systems: application to timing optimization of asynchronous circuits. | Jordi Cortadella, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Alexander Taubin, Alexandre Yakovlev |
| 1998 | Noise considerations in circuit optimization. | Andrew R. Conn, Ruud A. Haring, Chandramouli Visweswariah |
| 1998 | Delay-oriented technology mapping for heterogeneous FPGAs with bounded resources. | Jason Cong, Songjie Xu |
| 1998 | Multiway partitioning with pairwise movement. | Jason Cong, Sung Kyu Lim |
| 1998 | Fanout optimization under a submicron transistor-level delay model. | Pasquale Cocchini, Massoud Pedram, Gianluca Piccinini, Maurizio Zamboni |
| 1998 | A general approach for regularity extraction in datapath circuits. | Amit Chowdhary, Sudhakar Kale, Phani K. Saripella, Naresh Sehgal, Rajesh K. Gupta |
| 1998 | A graph-partitioning-based approach for multi-layer constrained via minimization. | Yih-Chih Chou, Youn-Long Lin |
| 1998 | Control generation for embedded systems based on composition of modal processes. | Pai H. Chou, Ken Hines, Kurt Partridge, Gaetano Borriello |
| 1998 | Synthesis of application specific instructions for embedded DSP software. | Hoon Choi, Seung Ho Hwang, Chong-Min Kyung, In-Cheol Park |
| 1998 | Estimation of power sensitivity in sequential circuits with power macromodeling application. | Zhanping Chen, Kaushik Roy, Edwin K. P. Chong |
| 1998 | Architecture driven circuit partitioning. | Chau-Shen Chen, TingTing Hwang, C. L. Liu |
| 1998 | Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation. | Chung-Ping Chen, Chris C. N. Chu, D. F. Wong |
| 1998 | Graph matching-based algorithms for FPGA segmentation design. | Yao-Wen Chang, Jai-Ming Lin, D. F. Wong |
| 1998 | Tight integration of combinational verification methods. | Jerry R. Burch, Vigyan Singhal |