| 1997 | Timing analysis based on primitive path delay fault identification. | Mukund Sivaraman, Andrzej J. Strojwas |
| 1997 | Symbolic analysis of large analog circuits with determinant decision diagrams. | Chuanjin Richard Shi, Xiang-Dong Tan |
| 1997 | Global harmony: coupled noise analysis for full-chip RC interconnect networks. | Kenneth L. Shepard, Vinod Narayanan, Peter C. Elmendorf, Gutuan Zheng |
| 1997 | Functional simulation using binary decision diagrams. | Christoph Scholl, Rolf Drechsler, Bernd Becker |
| 1997 | Simulated quenching: a new placement method for module generation. | Shinji Sato |
| 1997 | NRG: global and detailed placement. | Majid Sarrafzadeh, Maogang Wang |
| 1997 | Optimizing computations in a transposed direct form realization of floating-point LTI-FIR systems. | Naushik Sankarayya, Kaushik Roy, Debashis Bhattacharya |
| 1997 | Achievable bounds on signal transition activity. | Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj |
| 1997 | Generalized resource sharing. | Salil Raje, Reinaldo A. Bergamaschi |
| 1997 | Built-in test generation for synchronous sequential circuits. | Irith Pomeranz, Sudhakar M. Reddy |
| 1997 | A test synthesis technique using redundant register transfers. | Christos A. Papachristou, Mikhail Baklashov |
| 1997 | Exploiting off-chip memory access modes in high-level synthesis. | Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau |
| 1997 | PRIMA: passive reduced-order interconnect macromodeling algorithm. | Altan Odabasioglu, Mustafa Celik, Lawrence T. Pileggi |
| 1997 | Multipoint Pad approximation using a rational block Lanczos algorithm. | Tuyen V. Nguyen, Jing Li |
| 1997 | State transformation in event driven explicit simulation. | Tuyen V. Nguyen, Anirudh Devgan |
| 1997 | High-level area and power estimation for VLSI circuits. | Mahadevamurty Nemani, Farid N. Najm |
| 1997 | Reachability analysis using partitioned-ROBDDs. | Amit Narayan, Adrian J. Isles, Jawahar Jain, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
| 1997 | Low power logic synthesis for XOR based circuits. | Unni Narayanan, C. L. Liu |
| 1997 | Real time analysis and priority scheduler generation for hardware-software systems with a synthesized run-time system. | Vincent John Mooney III, Giovanni De Micheli |
| 1997 | Scheduling and binding bounds for RT-level symbolic execution. | Chuck Monahan, Forrest Brewer |
| 1997 | An output encoding problem and a solution technique. | Subhasish Mitra, LaNae J. Avra, Edward J. McCluskey |
| 1997 | Sequential optimisation without state space exploration. | Amit Mehrotra, Shaz Qadeer, Vigyan Singhal, Robert K. Brayton, Adnan Aziz, Alberto L. Sangiovanni-Vincentelli |
| 1997 | Transformational partitioning for co-design of multiprocessor systems. | Gilberto Fernandes Marchioro, Jean-Marc Daveau, Ahmed Amine Jerraya |
| 1997 | Minimum area retiming with equivalent initial states. | Naresh Maheshwari, Sachin S. Sapatnekar |
| 1997 | An exact solution to simultaneous technology mapping and linear placement problem. | Jinan Lou, Amir H. Salek, Massoud Pedram |