| 1996 | VERILAT: verification using logic augmentation and transformations. | Dhiraj K. Pradhan, Debjyoti Paul, Mitrajit Chatterjee |
| 1996 | Embedded tutorial: Speed - new paradigms in design for performance. | Ralph H. J. M. Otten, Lukas P. P. P. van Ginneken, Narendra V. Shenoy |
| 1996 | Buffered Steiner tree construction with wire sizing for interconnect layout optimization. | Takumi Okamoto, Jason Cong |
| 1996 | Partitioned ROBDDs - a compact, canonical and efficiently manipulable representation for Boolean functions. | Amit Narayan, Jawahar Jain, Masahiro Fujita, Alberto L. Sangiovanni-Vincentelli |
| 1996 | Static timing analysis for self resetting circuits. | Vinod Narayanan, Barbara A. Chappell, Bruce M. Fleischer |
| 1996 | Module placement on BSG-structure and IC layout applications. | Shigetoshi Nakatake, Kunihiro Fujiyoshi, Hiroshi Murata, Yoji Kajitani |
| 1996 | Generation of BDDs from hardware algorithm descriptions. | Shin-ichi Minato |
| 1996 | Accurate interconnect modeling: towards multi-million transistor chips as microwave circuits. | N. P. van der Meijs, T. Smedes |
| 1996 | Exploiting regularity for low-power design. | Renu Mehra, Jan M. Rabaey |
| 1996 | Simulation and sensitivity analysis of transmission line circuits by the characteristics method. | Jun-Fa Mao, Janet Meiling Wang, Ernest S. Kuh |
| 1996 | Design for manufacturability in submicron domain. | Wojciech Maly, Hans T. Heineken, Jitendra Khare, Pranab K. Nag |
| 1996 | Minimum replication min-cut partitioning. | Wai-Kei Mak, D. F. Wong |
| 1996 | ABILBO: Analog BuILt-in Block Observer. | Marcelo Lubaszewski, Salvador Mir, Leandro Pulz |
| 1996 | A power modeling and characterization method for the CMOS standard cell library. | Jiing-Yuan Lin, Wen-Zen Shen, Jing-Yang Jou |
| 1996 | Design of robust test criteria in analog testing. | Walter M. Lindermeir |
| 1996 | Algorithms for address assignment in DSP code generation. | Rainer Leupers, Peter Marwedel |
| 1996 | Clock tree synthesis for multi-chip modules. | Daksh Lehther, Sachin S. Sapatnekar |
| 1996 | Basic concepts for an HDL reverse engineering tool-set. | Gunther Lehmann, Bernhard Wunder, Klaus D. Mller-Glaser |
| 1996 | Comparing models of computation. | Edward A. Lee, Alberto L. Sangiovanni-Vincentelli |
| 1996 | Tearing based automatic abstraction for CTL model checking. | Woohyuk Lee, Abelardo Pardo, Jae-Young Jang, Gary D. Hachtel, Fabio Somenzi |
| 1996 | Intranets and EDA: impact, application, and technology. | David C. Ku, James A. Rowson |
| 1996 | Driving toward higher IDDQ test quality for sequential circuits: a generalized fault model and its ATPG. | Hisashi Kondo, Kwang-Ting Cheng |
| 1996 | Digital sensitivity: predicting signal interaction using functional analysis. | Desmond Kirkpatrick, Alberto L. Sangiovanni-Vincentelli |
| 1996 | Heterogeneous built-in resiliency of application specific programmable processors. | Kyosun Kim, Ramesh Karri, Miodrag Potkonjak |
| 1996 | Efficient time-domain simulation of frequency-dependent elements. | Sharad Kapur, David E. Long, Jaijeet S. Roychowdhury |