| 1996 | Analytical delay models for VLSI interconnects under ramp input. | Andrew B. Kahng, Kei Masuko, Sudhakar Muddu |
| 1996 | Clock-driven performance optimization in interactive behavioral synthesis. | Hsiao-Ping Juan, Daniel Gajski, Viraphol Chaiyakul |
| 1996 | Sensitivity analysis of iterative design processes. | Eric W. Johnson, Jay B. Brockman |
| 1996 | Metamorphosis: state assignment by retiming and re-encoding. | Balakrishnan Iyer, Maciej J. Ciesielski |
| 1996 | CTL model checking based on forward state traversal. | Hiroaki Iwashita, Tsuneo Nakata, Fumiyasu Hirose |
| 1996 | An iterative area/performance trade-off algorithm for LUT-based FPGA technology mapping. | Juinn-Dar Huang, Jing-Yang Jou, Wen-Zen Shen |
| 1996 | Enhancing high-level control-flow for improved testability. | Frank F. Hsu, Elizabeth M. Rudnick, Janak H. Patel |
| 1996 | Statistical sampling and regression analysis for RT-level power evaluation. | Cheng-Ta Hsieh, Qing Wu, Chih-Shun Ding, Massoud Pedram |
| 1996 | A novel dimension reduction technique for the capacitance extraction of 3D VLSI interconnects. | Wei Hong II, Weikai Sun, Zhenhai Zhu, Hao Ji, Ben Song, Wayne Wei-Ming Dai |
| 1996 | Power optimization in disk-based real-time application specific systems. | Inki Hong, Miodrag Potkonjak |
| 1996 | Validation coverage analysis for complex digital designs. | Richard C. Ho, Mark Horowitz |
| 1996 | SIGMA: a simulator for segment delay faults. | Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal |
| 1996 | Interconnect yield model for manufacturability prediction in synthesis of standard cell based designs. | Hans T. Heineken, Wojciech Maly |
| 1996 | Identification of unsettable flip-flops for partial scan and faster ATPG. | Ismed Hartanto, Vamsi Boppana, W. Kent Fuchs |
| 1996 | Width minimization of two-dimensional CMOS cells using integer programming. | Avaneendra Gupta, John P. Hayes |
| 1996 | A design for testability technique for RTL circuits using control/data flow extraction. | Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha |
| 1996 | Reduced-order modeling of large passive linear circuits by means of the SYPVL algorithm. | Roland W. Freund, Peter Feldmann |
| 1996 | Hierarchical statistical characterization of mixed-signal circuits using behavioral modeling. | Eric Felt, Stefano Zanella, Carlo Guardiani, Alberto L. Sangiovanni-Vincentelli |
| 1996 | Computation of circuit waveform envelopes using an efficient, matrix-decomposed harmonic balance algorithm. | Peter Feldmann, Jaijeet S. Roychowdhury |
| 1996 | A hierarchical functional structuring and partitioning approach for multiple-FPGA implementations. | Wen-Jong Fang, Allen C.-H. Wu |
| 1996 | VLSI circuit partitioning by cluster-removal using iterative improvement techniques. | Shantanu Dutt, Wenyong Deng |
| 1996 | Stratified random sampling for power estimation. | Chih-Shun Ding, Cheng-Ta Hsieh, Qing Wu, Massoud Pedram |
| 1996 | An observability-based code coverage metric for functional simulation. | Srinivas Devadas, Abhijit Ghosh, Kurt Keutzer |
| 1996 | Automatic netlist extraction for measurement-based characterization of off-chip interconnect. | Steven D. Corey, Andrew T. Yang |
| 1996 | Optimization of custom MOS circuits by transistor sizing. | Andrew R. Conn, Paula K. Coulman, Ruud A. Haring, Gregory L. Morrill, Chandramouli Visweswariah |