| 1996 | An efficient approach to simultaneous transistor and interconnect sizing. | Jason Cong, Lei He |
| 1996 | Expected current distributions for CMOS circuits. | Dennis J. Ciplickas, Ronald A. Rohrer |
| 1996 | An algorithm for synthesis of system-level interface circuits. | Ki-Seok Chung, Rajesh K. Gupta, C. L. Liu |
| 1996 | Optimal non-uniform wire-sizing under the Elmore delay model. | Chung-Ping Chen, Hai Zhou, D. F. Wong |
| 1996 | A coloring approach to the structural diagnosis of interconnects. | Xiao-Tao Chen, Fabrizio Lombardi |
| 1996 | ACV: an arithmetic circuit verifier. | Yirng-An Chen, Randal E. Bryant |
| 1996 | Synthesis using sequential functional modules (SFMs). | Samit Chaudhuri, Michael Quayle |
| 1996 | Generalized constraint generation in the presence of non-deterministic parasitics. | Edoardo Charbon, Paolo Miliozzi, Enrico Malavasi, Alberto L. Sangiovanni-Vincentelli |
| 1996 | Semi-analytical techniques for substrate characterization in the design of mixed-signal ICs. | Edoardo Charbon, Ranjit Gharpurey, Alberto L. Sangiovanni-Vincentelli, Robert G. Meyer |
| 1996 | Fast Boolean optimization by rewiring. | Shih-Chieh Chang, Lukas P. P. P. van Ginneken, Malgorzata Marek-Sadowska |
| 1996 | An efficient, bus-layout based method for early diagnosis of bussed driver shorts in printed circuit boards. | Kanad Chakraborty, Pinaki Mazumder |
| 1996 | A general dispersive multiconductor transmission line model for interconnect simulation in SPICE. | Mustafa Celik, Andreas C. Cangellaris |
| 1996 | Sequential redundancy identification using recursive learning. | Wanlin Cao, Dhiraj K. Pradhan |
| 1996 | Timing verification of sequential domino circuits. | David Van Campenhout, Trevor N. Mudge, Karem A. Sakallah |
| 1996 | Improved reachability analysis of large finite state machines. | Gianpiero Cabodi, Paolo Camurati, Stefano Quer |
| 1996 | Inaccuracies in power estimation during logic synthesis. | Daniel Brand, Chandramouli Visweswariah |
| 1996 | Integrated fault diagnosis targeting reduced simulation. | Vamsi Boppana, W. Kent Fuchs |
| 1996 | Directional bias and non-uniformity in FPGA global routing architectures. | Vaughn Betz, Jonathan Rose |
| 1996 | Hierarchical partitioning. | Dirk Behrens, Klaus Harbich, Erich Barke |
| 1996 | Using complete-1-distinguishability for FSM equivalence checking. | Pranav Ashar, Aarti Gupta, Sharad Malik |
| 1996 | Polarized observability don't cares. | Harm Arts, Michel R. C. M. Berkelaar, C. A. J. van Eijk |
| 1996 | Zamlog: a parallel algorithm for fault simulation based on Zambezi. | Minesh B. Amin, Bapiraju Vinnakota |
| 1996 | Compact and complete test set generation for multiple stuck-faults. | Alok Agrawal, Alexander Saldanha, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli |
| 1995 | A fast wavelet collocation method for high-speed VLSI circuit simulation. | D. Zhou, N. Chen, W. Cai |
| 1995 | Architectural partitioning of control memory for application specific programmable processors. | Wei Zhao, Christos A. Papachristou |