| 1995 | Single-layer fanout routing and routability analysis for Ball Grid Arrays. | Man-Fai Yu, Wayne Wei-Ming Dai |
| 1995 | Communication synthesis for distributed embedded systems. | Ti-Yen Yen, Wayne H. Wolf |
| 1995 | New algorithms for min-cut replication in partitioned circuits. | Hannah Honghua Yang, D. F. Wong |
| 1995 | Hierarchical timing analysis using conditional delays. | Hakan Yalcin, John P. Hayes |
| 1995 | Post routing performance optimization via multi-link insertion and non-uniform wiresizing. | Tianxiong Xue, Ernest S. Kuh |
| 1995 | Gate-level simulation of digital circuits using multi-valued Boolean algebras. | Scott Woods, Giorgio Casinovi |
| 1995 | PARAS: system-level concurrent partitioning and scheduling. | Wing Hang Wong, Rajiv Jain |
| 1995 | Multi-level logic optimization of FSM networks. | Huey-Yih Wang, Robert K. Brayton |
| 1995 | SUBTRACT: a program for the efficient evaluation of substrate parasitics in integrated circuits. | Nishath K. Verghese, David J. Allstot |
| 1995 | Delay optimal partitioning targeting low power VLSI circuits. | Hirendu Vaishnav, Massoud Pedram |
| 1995 | Switching activity analysis using Boolean approximation method. | Taku Uchino, Fumihiro Minami, Takashi Mitsuhashi, Nobuyuki Goto |
| 1995 | Relaxation-based harmonic balance technique for semiconductor device simulation. | Boris Troyanovsky, Zhiping Yu, Lydia So, Robert W. Dutton |
| 1995 | Estimation of maximum transition counts at internal nodes in CMOS VLSI circuits. | Chin-Chi Teng, Anthony M. Hill, Sung-Mo Kang |
| 1995 | Activity-driven clock design for low power circuits. | Gustavo E. Tllez, Amir H. Farrahi, Majid Sarrafzadeh |
| 1995 | Memory bank and register allocation in software synthesis for ASIPs. | Ashok Sudarsanam, Sharad Malik |
| 1995 | Impulse response fault model and fault extraction for functional level analog circuit diagnosis. | Chauchin Su, Shenshung Chiang, Shyh-Jye Jou |
| 1995 | Test register insertion with minimum hardware cost. | Albrecht P. Stroele, Hans-Joachim Wunderlich |
| 1995 | Extraction of circuit models for substrate cross-talk. | T. Smedes, N. P. van der Meijs, Arjan J. van Genderen |
| 1995 | Extracting RTL models from transistor netlists. | K. J. Singh, P. A. Subrahmanyam |
| 1995 | An optimal algorithm for area minimization of slicing floorplans. | Weiping Shi |
| 1995 | Address generation for memories containing multiple arrays. | Herman Schmit, Donald E. Thomas |
| 1995 | Logic synthesis for look-up table based FPGAs using functional decomposition and support minimization. | Hiroshi Sawada, Takayuki Suyama, Akira Nagoya |
| 1995 | Speeding up pipelined circuits through a combination of gate sizing and clock skew optimization. | Harsha Sathyamurthy, Sachin S. Sapatnekar, John P. Fishburn |
| 1995 | Power vs. delay in gate sizing: conflicting objectives? | Sachin S. Sapatnekar, Weitong Chuang |
| 1995 | Time-Constrained Loop Pipelining. | Fermn Snchez |