| 1995 | High-density reachability analysis. | Kavita Ravi, Fabio Somenzi |
| 1995 | An iterative improvement algorithm for low power data path synthesis. | Anand Raghunathan, Niraj K. Jha |
| 1995 | Acceleration techniques for dynamic vector compaction. | Anand Raghunathan, Srimat T. Chakradhar |
| 1995 | Cost optimization in ASIC implementation of periodic hard-real time systems using behavioral synthesis techniques. | Miodrag Potkonjak, Wayne H. Wolf |
| 1995 | Design-for-debugging of application specific designs. | Miodrag Potkonjak, Sujit Dey, Kazutoshi Wakabayashi |
| 1995 | Functional test generation for delay faults in combinational circuits. | Irith Pomeranz, Sudhakar M. Reddy |
| 1995 | Coping with RC(L) interconnect design headaches. | Lawrence T. Pileggi |
| 1995 | Statistical behavioral modeling and characterization of A/D converters. | Eduardo J. Peralas, Adoracin Rueda, Jos Luis Huertas |
| 1995 | Push-up scheduling: Optimal polynomial-time resource constrained scheduling for multi-dimensional applications. | Nelson L. Passos, Edwin Hsing-Mean Sha |
| 1995 | Who are the variables in your neighborhood. | Shipra Panda, Fabio Somenzi |
| 1995 | Pseudo-random testing and signature analysis for mixed-signal circuits. | Chen-Yang Pan, Kwang-Ting Cheng |
| 1995 | Power estimation techniques for integrated circuits. | Farid N. Najm |
| 1995 | Performance-driven simultaneous place and route for island-style FPGAs. | Sudip K. Nag, Rob A. Rutenbar |
| 1995 | Rectangle-packing-based module placement. | Hiroshi Murata, Kunihiro Fujiyoshi, Shigetoshi Nakatake, Yoji Kajitani |
| 1995 | On testable multipliers for fixed-width data path architectures. | Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer |
| 1995 | A sequential quadratic programming approach to concurrent gate and wire sizing. | Noel Menezes, Ross Baldick, Lawrence T. Pileggi |
| 1995 | Synthesis of multiplier-less FIR filters with minimum number of additions. | Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh |
| 1995 | Fast discrete function evaluation using decision diagrams. | Patrick C. McGeer, Kenneth L. McMillan, Alexander Saldanha, Alberto L. Sangiovanni-Vincentelli, Patrick Scaglia |
| 1995 | Re-engineering of timing constrained placements for regular architectures. | Anmol Mathur, Kuang-Chien Chen, C. L. Liu |
| 1995 | Board-level multi-terminal net routing for FPGA-based logic emulation. | Wai-Kei Mak, D. F. Wong |
| 1995 | A gradient method on the initial partition of Fiduccia-Mattheyses algorithm. | Lung-Tien Liu, Ming-Ter Kuo, Shih-Chen Huang, Chung-Kuan Cheng |
| 1995 | CAD challenges in multimedia computing. | Paul E. R. Lippens, Vijay Nagasamy, Wayne H. Wolf |
| 1995 | Cost-free scan: a low-overhead scan path design methodology. | Chih-Chang Lin, Mike Tien-Chien Lee, Malgorzata Marek-Sadowska, Kuang-Chien Chen |
| 1995 | Design based analog testing by Characteristic Observation Inference. | Walter M. Lindermeir, Helmut E. Graeb, Kurt Antreich |
| 1995 | Performance estimation of embedded software with instruction cache modeling. | Yau-Tsun Steven Li, Sharad Malik, Andrew Wolfe |