| 1995 | Optimal wire sizing and buffer insertion for low power and a generalized delay model. | John Lillis, Chung-Kuan Cheng, Ting-Ting Y. Lin |
| 1995 | Linear decomposition algorithm for VLSI design applications. | Jianmin Li, John Lillis, Chung-Kuan Cheng |
| 1995 | Instruction selection using binate covering for code size optimization. | Stan Y. Liao, Srinivas Devadas, Kurt Keutzer, Steven W. K. Tjiang |
| 1995 | Partitioning and reduction of RC interconnect networks based on scattering parameter macromodels. | Haifang Liao, Wayne Wei-Ming Dai |
| 1995 | Logic decomposition during technology mapping. | Eric Lehman, Yosinori Watanabe, Joel Grodstein, Heather Harkness |
| 1995 | PROP: a recursive paradigm for area-efficient and performance oriented partitioning of large FPGA netlists. | Roman Kuznar, Franc Brglez |
| 1995 | A novel methodology for statistical parameter extraction. | Kannan Krishna, Stephen W. Director |
| 1995 | Generating sparse partial inductance matrices with guaranteed stability. | Byron Krauter, Lawrence T. Pileggi |
| 1995 | A timing-driven data path layout synthesis with integer programming. | Jaewon Kim, Sung-Mo Kang |
| 1995 | Stable and efficient reduction of substrate model networks using congruence transforms. | Kevin J. Kerns, Ivan L. Wemple, Andrew T. Yang |
| 1995 | An empirical model for accurate estimation of routing delay in FPGAs. | Tanay Karnik, Sung-Mo Kang |
| 1995 | A new algorithm for the design of stable higher order single loop sigma delta analog-to-digital converters. | S. R. Kadivar, Doris Schmitt-Landsiedel, Heinrich Klar |
| 1995 | Background memory management for dynamic data structure intensive processing systems. | Gjalt G. de Jong, Bill Lin, Carl Verdonck, Sven Wuytack, Francky Catthoor |
| 1995 | Efficient validity checking for processor verification. | Robert B. Jones, David L. Dill, Jerry R. Burch |
| 1995 | Phantom redundancy: a high-level synthesis approach for manufacturability. | Balakrishnan Iyer, Ramesh Karri, Israel Koren |
| 1995 | Two-level logic minimization for low power. | Sasan Iman, Massoud Pedram |
| 1995 | Compatible class encoding in Roth-Karp decomposition for two-output LUT architecture. | Juinn-Dar Huang, Jing-Yang Jou, Wen-Zen Shen |
| 1995 | A single-path-oriented fault-effect propagation in digital circuits considering multiple-path sensitization. | Manfred Henftling, Hannes C. Wittmann, Kurt Antreich |
| 1995 | Pattern generation for a deterministic BIST scheme. | Sybille Hellebrand, Birgit Reeb, Steffen Tarnick, Hans-Joachim Wunderlich |
| 1995 | A formal approach to nonlinear analog circuit verification. | Lars Hedrich, Erich Barke |
| 1995 | Efficient construction of binary moment diagrams for verifying arithmetic circuits. | Kiyoharu Hamaguchi, Akihito Morita, Shuzo Yajima |
| 1995 | Constrained multivariable optimization of transmission lines with general topologies. | Rohini Gupta, Lawrence T. Pileggi |
| 1995 | A delay model for logic synthesis of continuously-sized networks. | Joel Grodstein, Eric Lehman, Heather Harkness, Bill Grundmann, Yosinori Watanabe |
| 1995 | On adaptive diagnostic test generation. | Yiming Gong, Sreejit Chakravarty |
| 1995 | Clock distribution design and verification for PowerPC microprocessors. | Shantanu Ganguly, Shervin Hojat |