| 1995 | Symbolic hazard-free minimization and encoding of asynchronous finite state machines. | Robert M. Fuhrer, Bill Lin, Steven M. Nowick |
| 1995 | APPlaUSE: Area and performance optimization in a unified placement and synthesis environment. | Elof Frank, Thomas Lengauer |
| 1995 | System partitioning to maximize sleep time. | Amir H. Farrahi, Majid Sarrafzadeh |
| 1995 | A controller-based design-for-testability technique for controller-data path circuits. | Sujit Dey, Vijay Gangaram, Miodrag Potkonjak |
| 1995 | Efficient and accurate transient simulation in charge-voltage plane. | Anirudh Devgan |
| 1995 | Dynamic test signal design for analog ICs. | Giri Devarayanadurg, Mani Soma |
| 1995 | A unified approach to topology generation and area optimization of general floorplans. | Parthasarathi Dasgupta, Susmita Sur-Kolay, Bhargab B. Bhattacharya |
| 1995 | A multiple-dominance switch-level model for simulation of short faults. | Peter Dahlgren |
| 1995 | A high-level design and optimization tool for analog RF receiver front-ends. | Jan Crols, Stphane Donnay, Michiel Steyaert, Georges G. E. Gielen |
| 1995 | Synthesizing Petri nets from state-based models. | Jordi Cortadella, Michael Kishinevsky, Luciano Lavagno, Alexandre Yakovlev |
| 1995 | Bounded-skew clock and Steiner routing under Elmore delay. | Jason Cong, Andrew B. Kahng, Cheng-Kok Koh, Chung-Wen Albert Tsao |
| 1995 | Optimal wiresizing for interconnects with multiple sources. | Jason Cong, Lei He |
| 1995 | Hybrid decision diagrams. | Edmund M. Clarke, Masahiro Fujita, Xudong Zhao |
| 1995 | Technology mapping for field-programmable gate arrays using integer programming. | Amit Chowdhary, John P. Hayes |
| 1995 | Efficient reduced-order modeling for the transient simulation of three-dimensional interconnect. | Mike Chou, Jacob K. White |
| 1995 | Statistical estimation of sequential circuit activity. | Tan-Li Chou, Kaushik Roy |
| 1995 | Interface co-synthesis techniques for embedded systems. | Pai H. Chou, Ross B. Ortega, Gaetano Borriello |
| 1995 | Diagnosis of realistic bridging faults with single stuck-at information. | Brian Chess, David B. Lavo, F. Joel Ferguson, Tracy Larrabee |
| 1995 | An iterative gate sizing approach with accurate delay evaluation. | Guangqiu Chen, Hidetoshi Onodera, Keikichi Tamaru |
| 1995 | Circuit partitioning with logic perturbation. | David Ihsin Cheng, Chih-Chang Lin, Malgorzata Marek-Sadowska |
| 1995 | Fault emulation: a new approach to fault grading. | Kwang-Ting Cheng, Shi-Yu Huang, Wei-Jin Dai |
| 1995 | LOT: logic optimization with testability-new transformations using recursive learning. | Mitrajit Chatterjee, Dhiraj K. Pradhan, Wolfgang Kunz |
| 1995 | Signal integrity optimization on the pad assignment for high-speed VLSI design. | Kai-Yuan Chao, D. F. Wong |
| 1995 | Binary decision diagrams and beyond: enabling technologies for formal verification. | Randal E. Bryant |
| 1995 | Be careful with don't cares. | Daniel Brand, Reinaldo A. Bergamaschi, Leon Stok |