| 1995 | Efficient orthonormality testing for synthesis with pass-transistor selectors. | Michel R. C. M. Berkelaar, Lukas P. P. P. van Ginneken |
| 1995 | Efficient use of large don't cares in high-level and logic synthesis. | Reinaldo A. Bergamaschi, Daniel Brand, Leon Stok, Michel R. C. M. Berkelaar, Shiv Prakash |
| 1995 | Timing analysis with known false sub graphs. | Krishna P. Belkhale, Alexander J. Suess |
| 1995 | Estimation and bounding of energy consumption in burst-mode control circuits. | Peter A. Beerel, Kenneth Y. Yun, Steven M. Nowick, Pei-Chuan Yeh |
| 1995 | Boolean techniques for low power driven re-synthesis. | R. Iris Bahar, Fabio Somenzi |
| 1995 | Sequential synthesis using S1S. | Adnan Aziz, Felice Balarin, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
| 1995 | Fast functional simulation using branching programs. | Pranav Ashar, Sharad Malik |
| 1995 | Design verification via simulation and automatic test pattern generation. | Hussain Al-Asaad, John P. Hayes |
| 1995 | Addressing high frequency effects in VLSI interconnects with full wave model and CFH. | Ramachandra Achar, Michel S. Nakhla, Qi-Jun Zhang |
| 1995 | The formal verification of a pipelined double-precision IEEE floating-point multiplier. | Mark D. Aagaard, Carl-Johan H. Seger |
| 1994 | Approximate symbolic analysis of large analog integrated circuits. | Qicheng Yu, Carl Sechen |
| 1994 | Performance-driven synthesis of asynchronous controllers. | Kenneth Y. Yun, Bill Lin, David L. Dill, Srinivas Devadas |
| 1994 | VLSI timing simulation with selective dynamic regionization. | Meng-Lin Yu, Bryan D. Ackland |
| 1994 | Edge-map: optimal performance driven technology mapping for iterative LUT based FPGA designs. | Hannah Honghua Yang, D. F. Wong |
| 1994 | Efficient network flow based min-cut balanced partitioning. | Honghua Yang, D. F. Wong |
| 1994 | On the NP-completeness of regular 2-D FPGA routing architectures and a novel solution. | Yu-Liang Wu, Douglas Chang |
| 1994 | An enhanced flow model for constraint handling in hierarchical multi-view design environments. | Pieter van der Wolf, K. Olav ten Bosch, Alfred van der Hoeven |
| 1994 | Low power state assignment targeting two-and multi-level logic implementations. | Chi-Ying Tsui, Massoud Pedram, Chih-Ang Chen, Alvin M. Despain |
| 1994 | Logic synthesis techniques for reduced area implementation of multilevel circuits with concurrent error detection. | Nur A. Touba, Edward J. McCluskey |
| 1994 | A simultaneous technology mapping, placement, and global routing algorithm for field-programmable gate arrays. | Nozomu Togawa, Masao Sato, Tatsuo Ohtsuki |
| 1994 | Power analysis of embedded software: a first step towards software power minimization. | Vivek Tiwari, Sharad Malik, Andrew Wolfe |
| 1994 | Folding a stack of equal width components. | Venkat Thanvantri, Sartaj K. Sahni |
| 1994 | Clock period constrained minimal buffer insertion in clock trees. | Gustavo E. Tllez, Majid Sarrafzadeh |
| 1994 | LP based cell selection with constraints of timing, area, and power consumption. | Yutaka Tamiya, Yusuke Matsunaga, Masahiro Fujita |
| 1994 | Adaptive cut line selection in min-cut placement for large scale sea-of-gates arrays. | Kazuhiro Takahashi, Kazuo Nakajima, Masayuki Terai, Koji Sato |