| 1994 | Fast timing simulation of transient faults in digital circuits. | Abhijit Dharchoudhury, Sung-Mo Kang, Hungse Cha, Janak H. Patel |
| 1994 | Non-scan design-for-testability of RT-level data paths. | Sujit Dey, Miodrag Potkonjak |
| 1994 | Analytical fault modeling and static test generation for analog ICs. | Giri Devarayanadurg, Mani Soma |
| 1994 | Time-domain non-Monte Carlo noise simulation for nonlinear dynamic circuits with arbitrary excitations. | Alper Demir, Edward W. Y. Liu, Alberto L. Sangiovanni-Vincentelli |
| 1994 | Multi-way VLSI circuit partitioning based on dual net representation. | Jason Cong, Wilburt Labio, Narayanan Shivakumar |
| 1994 | Simultaneous driver and wire sizing for performance and power optimization. | Jason Cong, Cheng-Kok Koh |
| 1994 | Dynamic scheduling and synchronization synthesis of concurrent digital systems under system-level constraints. | Claudionor Jos Nunes Coelho Jr., Giovanni De Micheli |
| 1994 | Skew sensitivity minimization of buffered clock tree. | Jae Chung, Chung-Kuan Cheng |
| 1994 | Delay and area optimization for compact placement by gate resizing and relocation. | Weitong Chuang, Ibrahim N. Hajj |
| 1994 | Estimation of circuit activity considering signal correlations and simultaneous switching. | Tan-Li Chou, Kaushik Roy, Sharat Prasad |
| 1994 | Random pattern testable logic synthesis. | Chen-Huan Chiang, Sandeep K. Gupta |
| 1994 | RISA: accurate and efficient placement routability modeling. | Chih-Liang Eric Cheng |
| 1994 | RAFT191486: a novel program for rapid-fire test and diagnosis of digital logic for marginal delays and delay faults. | Abhijit Chatterjee, Jacob A. Abraham |
| 1994 | Layer assignment for high-performance multi-chip modules. | Kai-Yuan Chao, D. F. Wong |
| 1994 | A new global routing algorithm for FPGAs. | Yao-Wen Chang, Shashidhar Thakur, Kai Zhu, D. F. Wong |
| 1994 | Perturb and simplify: multi-level boolean network optimizer. | Shih-Chieh Chang, Malgorzata Marek-Sadowska |
| 1994 | Boolean constrained encoding: a new formulation and a case study. | Ney Laert Vilar Calazans |
| 1994 | Optimization of critical paths in circuits with level-sensitive latches. | Timothy M. Burks, Karem A. Sakallah |
| 1994 | Incremental synthesis. | Daniel Brand, Anthony D. Drumm, Sandip Kundu, Prakash Narain |
| 1994 | Fault dictionary compaction by output sequence removal. | Vamsi Boppana, W. Kent Fuchs |
| 1994 | Provably correct high-level timing analysis without path sensitization. | Subhrajit Bhattacharya, Sujit Dey, Franc Brglez |
| 1994 | Computing the entire active area/power consumption versus delay trade-off curve for gate sizing with a piecewise linear simulator. | Michel R. C. M. Berkelaar, Pim H. W. Buurman, Jochen A. G. Jess |
| 1994 | Dataflow-driven memory allocation for multi-dimensional signal processing systems. | Florin Balasa, Francky Catthoor, Hugo De Man |
| 1994 | Iterative algorithms for formal verification of embedded real-time systems. | Felice Balarin, Alberto L. Sangiovanni-Vincentelli |
| 1994 | Design exploration for high-performance pipelines. | Smita Bakshi, Daniel D. Gajski |