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On-Line Testing and Robust System Design

IOLTS

C

CORE rank

CORE rank (raw)

C

Fields of research

Computer Systems Engineering · Software Engineering

Papers indexed

1,346

2000–2026

Papers per year

200069 peak2026

IOLTS papers

1,346 records sourced from DBLP. Search titles, filter by year, sort by recency.

YearTitleAuthors
2026Project Highlights - Reliability Evaluation for ARCHYTAS AI hardware accelerators.Angeliki Kritikakou, Fernando Fernandes dos Santos, Marcello Traiola, Rafael Billig Tonetto, Olivier Sentieys, Paolo Rech, Haralampos-G. Stratigopoulos, Giorgos Keramidas
2026Variation-Aware Training and Post-Manufacture Tuning of ReRAM Crossbar-Based Hyperdimensional Computing Systems.Sai Pranav Komaragiri, Anurup Saha, Mohamed Mejri, Abhijit Chatterjee
2026Interpretable GNNs for Fault Detection in Circuits.Rupesh Raj Karn, Johann Knechtel, Ozgur Sinanoglu
2026Structural Security Entropy: A Novel Prior for Robust GNN-Based Security Assessment of Netlists.Rupesh Raj Karn, Johann Knechtel, Ozgur Sinanoglu
2026Error-Resilient State-Space Networks Using Low-Precision Recovery Models.Jackson Isenberg, Mohamed Mejri, Abhijit Chatterjee
2026Optimizing Scan Test Economics Trade-Offs in Homogeneous 3D SICs via Cost Modeling.Giusy Iaria, Paolo Bernardi, Claudia Bertani, Giuseppe Garozzo, Vincenzo Tancorre
2026Runtime BIST for ReRAM-based CAM using Frequency-Domain Monitoring.Haneen G. Hezayyin, Mehdi B. Tahoori
2026DRsam: Detection of Fault-Based Microarchitectural Side-Channel Attacks in RISC-V Using Statistical Preprocessing and Association Rule Mining.Muhammad Hassan, Maria Mushtaq, Jaan Raik, Tara Ghasempouri
2026SHOUT-Trainer: Closed-loop Trainer for Silent Data Corruption Hunting and Observation Using Transformers.Seyedeh Maryam Ghasemi, Shanmukha Mangadahalli Siddaramu, Mehdi B. Tahoori
2026Exploring microarchitectural information from SoC communication buses to detect firmware corruption.Lucas Georget, Vincent Migliore, Vincent Nicomette, Philippe Leleux, Arthur Villard, Frdric Silvi
2026From Prompts to Pressure: Evaluating LLM-driven Agents for GPU Stress-code Generation.Aurora Gensale, Giuseppe Esposito, Juan-David Guerrero-Balaguera, Josie E. Rodriguez Condia, Luca Cagliero, Matteo Sonza Reorda
2026A Statistical Test Methodology for MTJ Stochastic Neurons in Neuromorphic Hardware.Jesus Gamez, Vctor H. Champac, Elena-Ioana Vatajelu, Leticia Bolzani Poehls
2026Asymmetric Transistor Aging in Modern Accelerators: Reliability Challenges, Vulnerabilities, and Mitigation Strategies.Freddy Gabbay, Firas Ramadan
2026Accelerated Dynamic Voltage Drop Prediction Using a Lightweight Machine Learning Model.Freddy Gabbay, Ido Parchomovsky, Itay Yonatanov, Mohammad Omri
2026ELP: Elastic Lifetime Processors for Improving Server Energy Efficiency.Freddy Gabbay, Jawad Haj-Yahya, Firas Ramadan, Majd Ganaiem, Panagiota Nikolaou, Yiannakis Sazeides
2026VeriSide-II: Structure-Aware Power Modeling for Side-Channel Analysis at Register Transfer Level.Behnam Farnaghinejad, Annachiara Ruospo, Alessandro Savino, Stefano Di Carlo, Ernesto Snchez
2026RESIST : Structured Regularization from Weight Similarity to Weight Diversity for Improving Error Resilience of Neural Networks.Maryam Eslami, Salim Ullah, Akash Kumar
2026Server Life Extensions at Scale.Rhea Dutta, Harish Dattatraya Dixit, Santosh Kumar, Daniel Moore, Sriram Sankar
2026SVE-Based Acceleration of Homomorphic Encryption Arithmetic on ARM Neoverse Processors.Massimiliano Donati, Guido Falai, Samuele Bartorelli, Daniele Rossi, Sergio Saponara
2026Scalable Reliability Assessment of Vision Transformers on Systolic Arrays via Fault Propagation Analysis.Natalia Cherezova, Artur Jutman, Maksim Jenihhin
2026CIM-FI: A HW-Aware Fault Injection Framework for Digital Compute-In-Memory DNN Accelerators.Panagiotis Chaidos, Alexis Maras, Theofilos Spyrou, Anteneh Gebregiorgis, Said Hamdioui, Dimitrios Soudris, Sotirios Xydis
2026Hardware-Aware Runtime Detection of Soft-Error Anomalies in DPU-Accelerated Neural Networks.Federico Buccellato, Corrado De Sio, Sarah Azimi, Luca Sterpone
2026RAS Enhancement of ECC-Protected Vector Register File for the RISC-V Architecture via RERI-Compliant Interface.Marcello Barbirotta, Nicasio Canino, Giovanni Mazzini, Mauro Olivieri, Daniele Rossi, Sergio Saponara
2026Evaluating Generative AI for Functional Safety Analysis of Integrated Circuits.Mouadh Ayache, Alessandra Nardi, Aditya Raj Singh, Brian Davenport, Ganapathy Parthasarathy, Teo Cupaiuolo, Mladen Berekovic, Saleh Mulhem
2026Microarchitectural Analysis of Speculative Execution Patterns in RISC-V using Machine Learning and ISA-Level Masking Wrappers.Muhammad Awais, Maria Mushtaq, Lirida Naviner, Jawad Haj-Yahya, Florent Bruguier
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