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On-Line Testing and Robust System Design

IOLTS

C

CORE rank

CORE rank (raw)

C

Fields of research

Computer Systems Engineering · Software Engineering

Papers indexed

1,346

2000–2026

Papers per year

200069 peak2026

IOLTS papers

1,346 records sourced from DBLP. Search titles, filter by year, sort by recency.

YearTitleAuthors
2009Variability and reliability-aware application tasks scheduling and power control (Voltage and Frequency Scaling) in the future nanoscale multiprocessors system on chip.Gilles Bizot, Nacer-Eddine Zergainoh, Michael Nicolaidis
2009Application-oriented SEU sensitiveness analysis of Atmel rad-hard FPGAs.Niccol Battezzati, Filomena Decuzzi, Massimo Violante, Michel Briet
2009Comparing transient-fault effects on synchronous and on asynchronous circuits.Rodrigo Possamai Bastos, Yannick Monnet, Gilles Sicard, Fernanda Lima Kastensmidt, Marc Renaudin, Ricardo Reis
2009Designing fault tolerant FSM by nano-PLA.Samary Baranov, Ilya Levin, Osnat Keren, Mark G. Karpovsky
2009Evaluating large grain TMR and selective partial reconfiguration for soft error mitigation in SRAM-based FPGAs.Jos Rodrigo Azambuja, Fernando Sousa, Lucas Rosa, Fernanda Lima Kastensmidt
2009A fast error correction technique for matrix multiplication algorithms.Costas Argyrides, Carlos Arthur Lang Lisba, Dhiraj K. Pradhan, Luigi Carro
2009Highs and lows of radiation testing.Dan Alexandrescu, Anne-Lise Lhomme-Perrot, Erwin Schfer, Cyrille Beltrando
2008On-Line Testing of Lab-on-Chip Using Digital Microfluidic Compactors.Yang Zhao, Krishnendu Chakrabarty
2008Self-Configuration and Reachability Metrics in Massively Defective Multiport Chips.Piotr Zajac, Jacques Henri Collet, Andrzej Napieralski
2008An Enhanced Logic BIST Architecture for Online Testing.Fan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz
2008A Systematical Method of Quantifying SEU FIT.Shi-Jie Wen, Dan Alexandrescu, Renaud Perez
2008Yield Improvement, Fault-Tolerance to the Rescue?.Julien Vial, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
2008Budget-Dependent Control-Flow Error Detection.Ramtilak Vemu, Jacob A. Abraham
2008Using Low Pass Filters in Mitigation Techniques against Single-Event Transients in 45nm Technology LSIs.Taiki Uemura, Ryo Tanabe, Yoshiharu Tosaka, Shigeo Satoh
2008Deterministic Built-in TPG with Segmented FSMs.Samara Sudireddy, Jayawant Kakade, Dimitri Kagaris
2008SRAM Cell Design Protected from SEU Upsets.Yuriy Shiyanovskii, Francis G. Wolff, Christos A. Papachristou
2008SystemC-Based Minimum Intrusive Fault Injection Technique with Improved Fault Representation.Rishad A. Shafik, Paul M. Rosinger, Bashir M. Al-Hashimi
2008Exploiting Parametric Power Supply and/or Temperature Variations to Improve Fault Tolerance in Digital Circuits.Jorge Semio, Judit Freijedo, Juan J. Rodrguez-Andina, Fabian Vargas, Marcelino B. Santos, Isabel C. Teixeira, Joo Paulo Teixeira
2008Soft Error Rates of Hardened Sequentials utilizing Local Redundancy.Norbert Seifert
2008Special Session 1: Radiation Hardening Techniques.Norbert Seifert
2008A Built-In Self-Test Scheme for Soft Error Rate Characterization.Alodeep Sanyal, Syed M. Alam, Sandip Kundu
2008Physical Demonstration of Polymorphic Self-Checking Circuits.Richard Ruzicka, Luks Sekanina, Roman Prokop
2008Communication Aware Recovery Configurations for Networks-on-Chip.Claudia Rusu, Cristian Grecu, Lorena Anghel
2008Growing Interest of Advanced Commercial CMOS Technologies for Space and Medical Applications. Illustration with a New Nano-Power and Radiation-Hardened SRAM in 130nm CMOS.Philippe Roche, Mark Lysinger, Gilles Gasiot, Jean-Marc Daveau, Mehdi Zamanian, Pierre Dautriche
2008New Linear SEC-DED Codes with Reduced Triple Bit Error Miscorrection Probability.Michael Richter, Klaus Oberlnder, Michael Gssel
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