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On-Line Testing and Robust System Design

IOLTS

C

CORE rank

CORE rank (raw)

C

Fields of research

Computer Systems Engineering · Software Engineering

Papers indexed

1,346

2000–2026

Papers per year

200069 peak2026

IOLTS papers

1,346 records sourced from DBLP. Search titles, filter by year, sort by recency.

YearTitleAuthors
2008Reliability in Application Specific Mesh-Based NoC Architectures.Fatemeh Refan, Homa Alemzadeh, Saeed Safari, Paolo Prinetto, Zainalabedin Navabi
2008False Error Study of On-line Soft Error Detection Mechanisms.M. Kiran Kumar Reddy, Bharadwaj S. Amrutur, Rubin A. Parekhji
2008Dynamic Testing of an SRAM-Based FPGA by Time-Resolved Laser Fault Injection.Vincent Pouget, Alexandre Douin, Gilles Foucard, Paul Peronnard, Dean Lewis, Pascal Fouillat, Raoul Velazco
2008Totally Fault Tolerant RNS Based FIR Filters.Salvatore Pontarelli, Gian Carlo Cardarilli, Marco Re, Adelio Salsano
2008Development of a Testbench for Validation of DMT and DT2 Fault-Tolerant Architectures on SOI PowerPC7448.Michel Pignol, Thierry Parrain, Vincent Claverie, Christian Bolat, Guy Estaves
2008A Hybrid Approach to the Test of Cache Memory Controllers Embedded in SoCs.Wilson J. Prez H., Jaime Velasco-Medina, Danilo Ravotto, Edgar E. Snchez, Matteo Sonza Reorda
2008A BISR Architecture for Embedded Memories.Kiamal Z. Pekmestzi, Nicholas Axelos, Isidoros Sideris, Nikos K. Moshopoulos
2008A Modular Memory BIST for Optimized Memory Repair.Philipp hler, Alberto Bosio, Giorgio Di Natale, Sybille Hellebrand
2008Guided Probabilistic Checksums for Error Control in Low Power Digital-Filters.Muhammad Mudassar Nisar, Abhijit Chatterjee
2008Special Session 2: Benchmarking and Standardization in Software-Based SER Characterization: Towards an IEEE Task Force?Michael Nicolaidis
2008Soft Error Protection Techniques.Subhasish Mitra
2008Directed Random SBST Generation for On-Line Testing of Pipelined Processors.Andreas Merentitis, George Theodorou, Mihalis Giorgaras, Nektarios Kranitis
2008Fault Tolerant Reversible Finite Field Arithmetic Circuits.Jimson Mathew, Jawar Singh, Anas Abu Taleb, Dhiraj K. Pradhan
2008Design Techniques for Bit-Parallel Galois Field Multipliers with On-Line Single Error Correction and Double Error Detection.Jimson Mathew, Abusaleh M. Jabir, Dhiraj K. Pradhan
2008Software Self-Testing of a Symmetric Cipher with Error Detection Capability.Paolo Maistri, Cyril Excoffon, Rgis Leveugle
2008A Low-Cost Accumulator-Based Test Pattern Generation Architecture.Dimitris Magos, Ioannis Voyiatzis, Steffen Tarnick
2008Smart Hardening for Round-based Encryption Algorithms: Application to Advanced Encryption Standard.Celia Lpez-Ongil, Alejandro Jimnez-Horas, Marta Portela-Garca, Mario Garca-Valderas, Enrique San Milln, Luis Entrena
2008Variation of SRAM Alpha-Induced Soft Error Rate with Technology Node.Damien Leroy, Rmi Gaillard, Erwin Schfer, Cyrille Beltrando, Shi-Jie Wen, Richard Wong
2008Basic Architecture for Logic Self Repair.Tobias Koal, Heinrich Theodor Vierhaus
2008A Novel GA-Based High-Level Synthesis Technique to Enhance RT-Level Concurrent Testing.Naghmeh Karimi, Soheil Aminzadeh, Saeed Safari, Zainalabedin Navabi
2008Modeling and Simulation of Circuit Aging in Scaled CMOS Design.Yu (Kevin) Kao
2008Integrating Scan Design and Soft Error Correction in Low-Power Applications.Michael E. Imhof, Hans-Joachim Wunderlich, Christian G. Zoellin
2008Verification and Analysis of Self-Checking Properties through ATPG.Marc Hunger, Sybille Hellebrand
2008A New Radiation Hardened by Design Latch for Ultra-Deep-Sub-Micron Technologies.Zhengfeng Huang, Huaguo Liang
2008Soft-Error Vulnerability of Sub-100-nm Flip-Flops.Tino Heijmen
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