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On-Line Testing and Robust System Design

IOLTS

C

CORE rank

CORE rank (raw)

C

Fields of research

Computer Systems Engineering · Software Engineering

Papers indexed

1,346

2000–2026

Papers per year

200069 peak2026

IOLTS papers

1,346 records sourced from DBLP. Search titles, filter by year, sort by recency.

YearTitleAuthors
2007Spread in Alpha-Particle-Induced Soft-Error Rate of 90-nm Embedded SRAMs.Tino Heijmen
2007Essential Fault-Tolerance Metrics for NoC Infrastructures.Cristian Grecu, Lorena Anghel, Partha Pratim Pande, Andr Ivanov, Resve A. Saleh
2007Tolerance to Small Delay Defects by Adaptive Clock Stretching.Swaroop Ghosh, Patrick Ndai, Swarup Bhunia, Kaushik Roy
2007On-Line Self-Healing of Circuits Implemented on Reconfigurable FPGAs.Manuel G. Gericota, Lus F. Lemos, Gustavo R. Alves, Jos M. Ferreira
2007A C-element Latch Scheme with Increased Transient Fault Tolerance for Asynchronous Circuits.K. T. Gardiner, Alexandre Yakovlev, Alexandre V. Bystrov
2007Architectural Trade-Offs for Fault Tolerant Multi-Core Systems.Krisztin Flautner
2007Blurring the Layers of Abstractions: Time to Take a Step Back?Krisztin Flautner
2007Robustness of circuits under delay-induced faults : test of AES with the PAFI tool.Olivier Faurax, Assia Tria, Laurent Freund, Frdric Bancel
2007Soft-Errors Phenomenon Impacts on Design for Reliability Technologies.Mark Derbey
2007An Analytical Model for Reliability Evaluation of NoC Architectures.Atefe Dalirsani, Mohammad Hosseinabady, Zainalabedin Navabi
2007Resilience, Production Yield and Self-Configuration in the Future Massively Defective Nanochips.Jacques Henri Collet, Piotr Zajac
2007Heavy Ion Test Results in a CMOS triple Voting Register for a High-Energy Physics Experiment.X. Cano, Sebasti A. Bota, Ricardo Graciani Diaz, David Gascon, A. Herms, Albert Comerma, Jaume Segura, Llus Garrido
2007Latchup effect in CMOS IC: a solution for crypto-processors protection against fault injection attacks?Nadine Buard, Florent Miller, Cdric Ruby, Rmi Gaillard
2007A Configurable Modular Test Processor and Scan Controller Architecture.R. Frost, D. Rudolph, Christian Galke, Ren Kothe, Heinrich Theodor Vierhaus
2007An Automated Methodology for Cogeneration of Test Blocks for Peripheral Cores.Letcia Maria Veiras Bolzani, Ernesto Snchez, Massimiliano Schillaci, Matteo Sonza Reorda, Giovanni Squillero
2007A Hybrid Approach to Fault Detection and Correction in SoCs.Paolo Bernardi, Letcia Maria Veiras Bolzani, Matteo Sonza Reorda
2007Online monitoring of FPGA-based co-processing engines embedded in dependable workstations.Nikolaos G. Bartzoudis, Klaus D. McDonald-Maier
2007Single Event Effects in 1Gbit 90nm NAND Flash Memories under Operating Conditions.Marta Bagatin, Giorgio Cellere, Simone Gerardin, Alessandro Paccagnella, Angelo Visconti, Silvia Beltrami, M. Maccarrone
2007Statistical Device Variability and its Impact on Yield and Performance.Asen Asenov
2007Highly Reliable Power Aware Memory Design.Costas Argyrides, Dhiraj K. Pradhan
2007A Functional Self-Test Approach for Peripheral Cores in Processor-Based SoCs.Andreas Apostolakis, Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis
2007An Elliptic Curve Cryptosystem Design Based on FPGA Pipeline Folding.Osama Daifallah Al-Khaleel, Christos A. Papachristou, Francis G. Wolff, Kiamal Z. Pekmestzi
2007Fuse: A Technique to Anticipate Failures due to Degradation in ALUs.Jaume Abella, Xavier Vera, Osman S. Unsal, Oguz Ergin, Antonio Gonzlez
2006A Partitioning Technique for Identification of Error-Capturing Scan Cells in Scan-BIST.Chaowen Yu, Sudhakar M. Reddy, Irith Pomeranz
2006Designing Robust Checkers in the Presence of Massive Timing Errors.Frederic Worm, Patrick Thiran, Paolo Ienne
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