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On-Line Testing and Robust System Design

IOLTS

C

CORE rank

CORE rank (raw)

C

Fields of research

Computer Systems Engineering · Software Engineering

Papers indexed

1,346

2000–2026

Papers per year

200069 peak2026

IOLTS papers

1,346 records sourced from DBLP. Search titles, filter by year, sort by recency.

YearTitleAuthors
2006Phase-Locked Loop Automatic Layout Generation and Transient Fault Injection Analysis: A Case Study.Cristiano Lazzari, Ricardo A. L. Reis, Lorena Anghel
2006An Improved Technique for Reducing False Alarms Due to Soft Errors.Sandip Kundu, Ilia Polian
2006Power Attacks on Secure Hardware Based on Early Propagation of Data.Konrad J. Kulikowski, Mark G. Karpovsky, Alexander Taubin
2006Fault Tolerant System Design Method Based on Self-Checking Circuits.Pavel Kubalk, Petr Fiser, Hana Kubtov
2006Online Testing by Protocol Decomposition.Deepali Koppad, Danil Sokolov, Alexandre V. Bystrov, Alexandre Yakovlev
2006A Low-Cost SEU Fault Emulation Platform for SRAM-Based FPGAs.P. Kenterlis, Nektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos, Mihalis Psarakis
2006Prediction of Transient Induced by Neutron/Proton in CMOS Combinational Logic Cells.Guillaume Hubert, Antonin Bougerol, Florent Miller, Nadine Buard, Lorena Anghel, Thierry Carrire, Frederic Wrobel, Rmi Gaillard
2006Secure Scan Techniques: A Comparison.David Hly, Frdric Bancel, Marie-Lise Flottes, Bruno Rouzeyre
2006Factors That Impact the Critical Charge of Memory Elements.Tino Heijmen, Damien Giot, Philippe Roche
2006Soft Error Rates in Deep-Submicron CMOS Technologies.Tino Heijmen
2006Built-in Self Repair by Reconfiguration of FPGAs.S. Habermann, Ren Kothe, Heinrich Theodor Vierhaus
2006On-line Fault Detection and Location for NoC Interconnects.Cristian Grecu, Andr Ivanov, Res Saleh, Egor S. Sogomonyan, Partha Pratim Pande
2006Delay Fault Localization in Test-Per-Scan BIST Using Built-In Delay Sensor.Swaroop Ghosh, Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy
2006Emulation-based Fault Injection in Circuits with Embedded Memories.Mario Garca-Valderas, Marta Portela-Garca, Celia Lpez-Ongil, Luis Entrena
2006Embedded Scan Test with Diagnostic Features for Self-Testing SoCs.Christian Galke, Ren Kothe, Sabine Schultke, K. Winkler, Jeanette Honko, Heinrich Theodor Vierhaus
2006Evaluating SEU and Crosstalk Effects in Network-on-Chip Routers.Arthur Pereira Frantz, Luigi Carro, rika F. Cota, Fernanda Lima Kastensmidt
2006Real Time Fault Injection Using a Modified Debugging Infrastructure.Andr V. Fidalgo, Gustavo R. Alves, Jos M. Ferreira
2006The Problem of On-Line Testing Methods In Approximate Data Processing.Alexander V. Drozd, M. V. Lobachev, Julia V. Drozd
2006The Challenge of Reliability in Future Complex Systems.Andrea Cuomo
2006Trends and Trade-offs in Designing Highly Robust Throughput on Chip Communication Network.Marcello Coppola
2006Contribution of Communications to Dependability in Massively-Defective General-Purpose Nanoarchitectures.Jacques Henri Collet, Piotr Zajac, Yves Crouzet, Andrzej Napieralski
2006Erratic Effects of Irradiation in Floating Gate Memory Cells.G. Cellere, Alessandro Paccagnella, Angelo Visconti, Mauro Bonanomi
2006Evaluating One-Hot Encoding Finite State Machines for SEU Reliability in SRAM-based FPGAs.Maico Cassel, Fernanda Lima Kastensmidt
2006Localization of Faults in Radix-n Signed Digit Adders.Gian Carlo Cardarilli, Marco Ottavi, Salvatore Pontarelli, Marco Re, Adelio Salsano
2006A Note on Error Detection in an RSA Architecture by Means of Residue Codes.Luca Breveglieri, Paolo Maistri, Israel Koren
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