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On-Line Testing and Robust System Design

IOLTS

C

CORE rank

CORE rank (raw)

C

Fields of research

Computer Systems Engineering · Software Engineering

Papers indexed

1,346

2000–2026

Papers per year

200069 peak2026

IOLTS papers

1,346 records sourced from DBLP. Search titles, filter by year, sort by recency.

YearTitleAuthors
2001Exploiting FPGA for Accelerating Fault Injection Experiments.Pierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
2001Automatic Bias Generation Using Pipeline Instruction State Coverage for Biased Random Instruction Generation.Mrinal Bose, Elizabeth M. Rudnick, Magdy S. Abadir
2001A Gated Clock Scheme for Low Power Scan-Based BIST.Yannick Bonhomme, Patrick Girard, Los Guiller, Christian Landrault, Serge Pravossoudovitch
2001Designing Reliable Embedded Systems Based on 32 Bit Microprocessors.Cristiana Bolchini, Fabio Salice, Donatella Sciuto
2001Reliability Properties Assessment at System Level: A Co-design Framework.Cristiana Bolchini, Luigi Pomante, Fabio Salice, Donatella Sciuto
2001Self-Stabilization Testing of LUT-Based FPGA Designs by Fault Injection.Michael Bhnel, Reinhold Weiss
2001Validation of a Software Dependability Tool via Fault Injection Experiments.Alfredo Benso, Stefano Di Carlo, Giorgio Di Natale, Luca Tagliaferri, Paolo Prinetto
2001Fault Diagnosis for Linear Analog Circuits with Symbolic Analysis and Reduced Observable Point Set.Marcello Artioli, Fiorenzo Filippetti
2001Novel Fault-Tolerant Adder Design for FPGA-Based Systems.Monica Alderighi, Sergio D'Angelo, Giacomo R. Sechi, Cecilia Metra
2001On-Line Testing in Continuous Operation of Embedded Systems: Modeling and Performance Evaluation.Chouki Aktouf
2001Path-Based Error Coverage Prediction.Joakim Aidemark, Peter Folkesson, Johan Karlsson
2001On-Line BIST and Diagnosis of FPGA Interconnect Using Roving STARs.Miron Abramovici, Charles E. Stroud, Matthew Lashinsky, Jeremy Nall, John Marty Emmert
2000Power Reduction in Test-Per-Scan BIST.Xiaodong Zhang, Kaushik Roy
2000Micro-Checkpointing: Checkpointing for Multithreaded Applications.Keith Whisnant, Zbigniew Kalbarczyk, Ravishankar K. Iyer
2000Transient Bitflip Injection in Microprocessor Embedded Applications.Raoul Velazco, Sana Rezgui
2000Estimating Circuit Fault-Tolerance by Means of Transient-Fault Injection in VHDL.Fabian Vargas, Alexandre M. Amory, Raoul Velazco
2000A Stamping Technique to Increase the Error Correction Capacity of the (127, k, d) RS Code.T. Vallino, Abbas Dandache, Jean-Paul Delahaye, Fabrice Monteiro, Bernard Lepley
2000A Compact Built-In Current Sensor for IDDQ Testing.Y. Tsiatouhas, Th. Haniotakis, Dimitris Nikolos
2000Improving Fault Coverage in System Tests.Janusz Sosnowski
2000Relation between Fault Tolerance and Reconfiguration in Cellular Systems.Luks Sekanina, Vladimr Drbek
2000Concurrent Scan Monitoring and Multi-Pattern Search.Jose Miguel Vieira dos Santos
2000A Crosstalk Sensor Implementation for Measuring Interferences in Digital CMOS VLSI Circuits.Jos Antonio Sainz, R. Muoz, J. A. Maiz, L. A. Aguado, Miquel Roca
2000Evaluating the Effectiveness of a Software Fault-Tolerance Technique on RISC- and CISC-Based Architectures.Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante, Ph. Cheynet, Bogdan Nicolescu, Raoul Velazco
2000An Overview of the Applications of a Pulsed Laser System for SEU Testing.Vincent Pouget, Pascal Fouillat, Dean Lewis, Herv Lapuyade, L. Sarger, F. M. Roche, S. Duzellier, R. Ecoffet
2000New Techniques for Accelerating Fault Injection in VHDL Descriptions.B. Parrotta, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
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