| 2009 | An outlier detection based approach for PCB testing. | Xin He, Yashwant K. Malaiya, Anura P. Jayasumana, Kenneth P. Parker, Stephen Hird |
| 2009 | Defect-oriented cell-aware ATPG and fault simulation for industrial cell libraries and designs. | Friedrich Hapke, Rene Krenz-Baath, Andreas Glowatz, Jrgen Schlffel, Hamidreza Hashempour, Stefan Eichenberger, Camelia Hora, Dan Adolfsson |
| 2009 | Cache-resident self-testing for I/O circuitry. | Sankar Gurumurthy, D. Bertanzetti, P. Jakobsen, Jeff Rearick |
| 2009 | Application of non-parametric statistics of the parametric response for defect diagnosis. | Rama Gudavalli, W. Robert Daasch, Phil Nigh, Douglas Heaberlin |
| 2009 | Comparing the effectiveness of deterministic bridge fault and multiple-detect stuck fault patterns for physical bridge defects: A simulation and silicon study. | Sandeep Kumar Goel, Narendra Devta-Prasanna, Mark Ward |
| 2009 | Test access mechanism for multiple identical cores. | Grady Giles, Jing Wang, Anuja Sehgal, Kedarnath J. Balakrishnan, James Wingfield |
| 2009 | Boundary-scan adoption - an industry snapshot with emphasis on the semiconductor industry. | Philip B. Geiger, Steve Butkovich |
| 2009 | Dynamic arbitrary jitter injection method for ≫6.5Gb/s SerDes testing. | Tasuku Fujibe, Masakatsu Suda, Kazuhiro Yamamoto, Yoshihito Nagata, Kazuhiro Fujita, Daisuke Watanabe, Toshiyuki Okayasu |
| 2009 | Test Mode Entry and Exit Methods for IEEE P1581 compliant devices. | Heiko Ehrenberg |
| 2009 | Minimizing outlier delay test cost in the presence of systematic variability. | Dragoljub Gagi Drmanac, Brendon Bolin, Li-C. Wang, Magdy S. Abadir |
| 2009 | Fast circuit topology based method to configure the scan chains in Illinois Scan architecture. | Swapneel Donglikar, Mainak Banga, Maheshwar Chandrasekar, Michael S. Hsiao |
| 2009 | Accurate measurement of small delay defect coverage of test patterns. | Narendra Devta-Prasanna, Sandeep Kumar Goel, Arun Gunda, Mark Ward, P. Krishnamurthy |
| 2009 | Fast extended test access via JTAG and FPGAs. | Sergei Devadze, Artur Jutman, Igor Aleksejev, Raimund Ubar |
| 2009 | Fine resolution double edge clipping with calibration technique for built-in at-speed delay testing. | Chen-I Chung, Shuo-Wen Chang, Ching-Hwa Cheng |
| 2009 | A novel test flow for one-time-programming applications of NROM technology. | Ching-Yu Chin, Yao-Te Tsou, Chi-Min Chang, Mango Chia-Tso Chao |
| 2009 | Data learning techniques and methodology for Fmax prediction. | Janine Chen, Li-C. Wang, Po-Hsien Chang, Jing Zeng, S. Yu, Michael Mateja |
| 2009 | Using transition test to understand timing behavior of logic circuits on UltraSPARC | Liang-Chi Chen, Paul Dickinson, Peter Dahlgren, Scott Davidson, Olivier Caty, Kevin Wu |
| 2009 | Speeding up bounded sequential equivalence checking with cross-timeframe state-pair constraints from data learning. | Chia-Ling Chang, Charles H.-P. Wen, Jayanta Bhadra |
| 2009 | Capture power reduction using clock gating aware test generation. | Krishna Chakravadhanula, Vivek Chickermane, Brion L. Keller, Patrick R. Gallagher Jr., Prashant Narang |
| 2009 | Test infrastructures evaluation at transaction level. | Stefano Di Carlo, Nadereh Hatami, Paolo Prinetto |
| 2009 | Feature based similarity search with application to speedpath analysis. | Nicholas Callegari, Li-C. Wang, Pouria Bastani |
| 2009 | Power scan: DFT for power switches in VLSI designs. | Bing-Chuan Bai, Chien-Mo James Li, Augusli Kifli, Even Tsai, Kun-Cheng Wu |
| 2009 | Microprocessor system failures debug and fault isolation methodology. | M. Enamul Amyeen, Srikanth Venkataraman, Mun Wai Mak |
| 2009 | Non-invasive RF built-in testing using on-chip temperature sensors. | Eduardo Aldrete-Vidrio, Marvin Onabajo, Josep Altet, Diego Mateo, Jos Silva-Martnez |
| 2008 | Built-in Self-Test and Fault Diagnosis for Lab-on-Chip Using Digital Microfluidic Logic Gates. | Yang Zhao, Tao Xu, Krishnendu Chakrabarty |