| 1995 | A C-testable modified Booth's array multiplier. | S. M. Aziz |
| 1995 | Logic minimization based approach for compressing image data. | Jacob Augustine, Wen Feng, James Jacob |
| 1995 | Design of a VLSI parallel processor for fuzzy computing. | Giuseppe Ascia, Vincenzo Catania |
| 1995 | A 16-bit x 16-bit 1.2 μ CMOS multiplier with low latency vector merging. | W. Amendola Jr., Hosahalli R. Srinivas, Keshab K. Parhi |
| 1995 | Exposing floating gate defects in analogue CMOS circuits by power supply voltage control testing technique. | Abu Khari bin A'Ain, A. H. Bratt, A. P. Dorey |
| 1994 | A SPICE Model of RLGC Transmission Line with Error Control. | Qingjian Yu, Omar Wing |
| 1994 | VLSI Architecture for HDTV Motion Estimation Based on Block-Matching Algorithm. | Feng-Ming Yang, Stefan Wolter, Rainer Laur |
| 1994 | An Optimal Design for Parallel Test Generation Based on Circuit Partitioning. | Dong Xiang, Daozheng Wei |
| 1994 | The Design of Analog Self-Checking Circuits. | Bapiraju Vinnakota, Ramesh Harjani |
| 1994 | Early Exploration of the Multi-Dimensional VLSI Design Space. | Mourad B. Takla, Donald W. Bouldin, Daniel B. Koch |
| 1994 | A Three-Stage Partial Scan Design Method Using the Sequential Circuit Flow Graph. | Shang-E Tai, Debashis Bhattacharya |
| 1994 | An Improved Deductive Fault Simulator. | P. R. Suresh Kumar, James Jacob, Mandyam-Komar Srinivas, Vishwani D. Agrawal |
| 1994 | Graphical Methodology Language for CAD Frameworks. | James Sienicki, Michael L. Bushnell, Sandip Parikh |
| 1994 | Logic Simulation Using an Asynchronous Parallel Discrete-Event Simulation Model on a SIMD Machine. | Sharad C. Seth, Lee Gowen, Matt Payne, Don Sylwester |
| 1994 | An Object Oriented Environment for Modeling and Synthesis of Hardware Circuits. | Santonu Sarkar, Anupam Basu |
| 1994 | A Sea-of-Gates Style FPGA Placement Algorithm. | Kalapi Roy-Neogi, Bingzhong Guan, Carl Sechen |
| 1994 | Simulated Annealing for Target-Oriented Scan. | C. P. Ravikumar, Haroon Rasheed |
| 1994 | A Methodology for Architecture Synthesis of Cascaded IIR Filters on TLU FPGAs. | G. N. Rathna, S. K. Nandy, K. Parthasarathy |
| 1994 | CM-SIM: A Parallel Circuit Simulator on a Distributed Memory Multiprocessor. | C. V. Ramamoorthy, Vikram Vij |
| 1994 | On Determining Symmetries in Inputs of Logic Circuits. | Irith Pomeranz, Sudhakar M. Reddy |
| 1994 | A Fast Algorithm for Performing Vector Quantization and its VLSI Implementation. | Heonchul Park, Viktor K. Prasanna |
| 1994 | Calculation of Minimum Number of Registers in Arbitrary Life Time Chart. | Keshab K. Parhi |
| 1994 | Untitled record | Srikanth Natarajan, Debapriya Sahu, Sattam Dasgupta |
| 1994 | FAST: FPGA Targeted RTL Structure Synthesis Technique. | A. R. Naseer, M. Balakrishnan, Anshul Kumar |
| 1994 | A CAD Tool for Design of On-Chip Store & Generate Scheme. | Sukumar Nandi, Vamsi Boppana, Parimal Pal Chaudhuri |