Skip to content

IEEE VLSI Test Symposium

VTS

National

CORE rank

CORE rank (raw)

National/Regional

Fields of research

Computer Systems Engineering

Papers indexed

2,208

1991–2026

Papers per year

199189 peak2026

VTS papers

2,208 records sourced from DBLP. Search titles, filter by year, sort by recency.

YearTitleAuthors
2017Innovative practices session 2C: "How is industry simplifying analog test".Rubin A. Parekhji, Srinivas Modekurty
2017Innovative practices session 4C data analytics in test.Suriya Natarajan, Abhijit Sathaye
2017On-line diagnosis and compensation for parametric failures in linear state variable circuits and systems using time-domain checksum observers.Md Imran Momtaz, Suvadeep Banerjee, Abhijit Chatterjee
2017Foreword.Yiorgos Makris, Srivaths Ravi, Amit Majumdar
2017Knob non-idealities in learning-based post-production tuning of analog/RF ICs: Impact & remedies.Yichuan Lu, Georgios Volanis, Kiruba S. Subramani, Angelos Antonopoulos, Yiorgos Makris
2017Aging monitor reuse for small delay fault testing.Chang Liu, Michael A. Kochte, Hans-Joachim Wunderlich
2017Innovative practices session 10C formal verification practices in industry.Huawei Li, Xiaowei Li
2017Test-cost optimization in a scan-compression architecture using support-vector regression.Zipeng Li, Jonathon E. Colburn, Vinod Pagalone, Kaushik Narayanun, Krishnendu Chakrabarty
2017Fast WAT test structure for measuring Vt variance based on latch-based comparators.Kao-Chi Lee, Kai-Chiang Wu, Chih-Ying Tsai, Mango Chia-Tso Chao
2017Fiscal: Firmware identification using side-channel power analysis.Deepak Krishnankutty, Ryan W. Robucci, Nilanjan Banerjee, Chintan Patel
2017A methodology for estimating memory lifetime using a system-level accelerated life test and error-correcting codes.Dae-Hyun Kim, Linda Milor
2017An analytical model for predicting the residual life of an IC and design of residual-life meter.Md. Nazmul Islam, Sandip Kundu
2017Structured scan patterns retargeting for dynamic instruments access.Ahmed Ibrahim, Hans G. Kerkhoff
2017Methodology of generating dual-cell-aware tests.Yu-Hao Huang, Ching-Ho Lu, Tse-Wei Wu, Yu-Teng Nien, Ying-Yen Chen, Max Wu, Jih-Nung Lee, Mango C.-T. Chao
2017Innovative practices session 11C SoC testing.Yu Huang
2017Innovative practices session 10B innovative practices in Asia-2: From cost perspective.Kazumi Hatayama, Masahiro Ishida
2017Innovative practices session 9B innovative practices in Asia-1: From quality perspective.Kazumi Hatayama, Masahiro Ishida
2017Keynote address tribute to Professor Mel Breuer: Contributions to CAD and Test.Sandeep Gupta, Miron Abramovici, Magdy Abadir, Sridhar Narayanan
2017A novel design-for-security (DFS) architecture to prevent unauthorized IC overproduction.Ujjwal Guin, Ziqi Zhou, Adit D. Singh
2017Innovative practices session 6C DFT for functional safety.Prashant Goteti, Sreejit Chakravarty
2017A framework for fast test generation at the RTL.Kelson Gent, Akash Agrawal, Michael S. Hsiao
2017Accurate jitter decomposition in high-speed links.Yan Duan, Degang Chen
2017Comprehensive investigation of gate oxide short in FinFETs.Roya Dibaj, Dhamin Al-Khalili, Maitham Shams
2017Special session on early life failures.Jyotirmoy V. Deshmukh, Wolfgang Kunz, Hans-Joachim Wunderlich, Sybille Hellebrand
2017Innovative practices session 9C DFT and data for diagnostics.Kun Young Chung, Stefano Di Carlo
501525 of 2,208← PreviousNext →

Comparable venues

Other A*/A conferences filed under the same field of research.