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IEEE VLSI Test Symposium

VTS

National

CORE rank

CORE rank (raw)

National/Regional

Fields of research

Computer Systems Engineering

Papers indexed

2,208

1991–2026

Papers per year

199189 peak2026

VTS papers

2,208 records sourced from DBLP. Search titles, filter by year, sort by recency.

YearTitleAuthors
2018Special session: Recent developments in hardware security.Ro Cammarota, Naghmeh Karimi, Siddharth Garg, Jeyavijayan Rajendran
2018A coherent subsampling test system arrangement suitable for phase domain measurements.Young Gouk Cho, Gordon W. Roberts, Sadok Aouini, Mahdi Parvizi, Naim Ben-Hamida
2018Special session on machine learning for test and diagnosis.Krishnendu Chakrabarty, Li-C. Wang, Gaurav Veda, Yu Huang
2018Innovative practices on memory test practice.M. Casarsa, Gurgen Harutyunyan, Kaitlyn Chen, Ramesh Sharma, Giri Podichetty, Martin Keim, Sreejit Chakravarty, Ramesh C. Tekumalla
2018Special session on intelligent sensor nodes.Kanad Basu, Shreyas Sen
2018Innovative practices on test in Japan.Koji Asami, Yoshiro Tamura, Haruo Kobayashi, Jun Matsushima, Yoichi Maeda, Kazumi Hatayama
2018Innovative practices on challenges, opportunities, and solutions to hardware security.Sohrab Aftabjahani, Jason Oberg, Michael Chen, Huawei Li
2017Asymmetric sizing: An effective design approach for SRAM cells against BTI aging.Xuan Zuo, Sandeep K. Gupta
2017Dynamically obfuscated scan for protecting IPs against scan-based attacks throughout supply chain.Dongrong Zhang, Miao Tony He, Xiaoxiao Wang, Mark Tehranipoor
2017HLDTL: High-performance, low-cost, and double node upset tolerant latch design.Aibin Yan, Zhengfeng Huang, Maoxiang Yi, Jie Cui, Huaguo Liang
2017Test-set reordering for improving diagnosability.Cheng Xue, R. D. (Shawn) Blanton
2017A new delay testing signal scheme robust to power distribution network impedance variation.Claude Thibeault, Ali Louati
2017Adaptive test flow for mixed-signal ICs.Haralampos-G. D. Stratigopoulos, Christian Streitwieser
2017Innovative practices session 1C screening for layout sensitive defects.Arani Sinha, Nitin Chaudhary
2017Learning the process for correlation analysis.Sebastian Siatkowski, Li-C. Wang, Nik Sumikawa, LeRoy Winemberg
2017Leveraging Systematic Unidirectional Error-Detecting Codes for fast STT-MRAM cache.Nour Sayed, Fabian Oboril, Rajendra Bishnoi, Mehdi Baradaran Tahoori
2017A technique for dynamic range improvement of intermodulation distortion products for an Interpolating DAC-based Arbitrary Waveform Generator using a phase switching algorithm.Peter Sarson, Shohei Shibuya, Tomonori Yanagida, Haruo Kobayashi
2017Innovative practices session 5C automotive test solutions.Pete Sarson, Stefano Di Carlo
2017Innovative practices session 7C automotive quality assurance.Peter Sarson
2017Analysis of an efficient on-chip servo-loop technique for reduced-code static linearity test of pipeline ADCs.Guillaume Renaud, Marc Margalef-Rovira, Manuel J. Barragn, Salvador Mir
2017Innovative practices session 4A variation-tolerant design of circuits/systems.Arijit Raychowdhury
2017Innovative practices session 3C hardware security.Jeyavijayan (JV) Rajendran, Peilin Song, Suriya Natarajan
2017An optimised SDD ATPG and SDQL computation method across different pattern sets.Wilson Pradeep, Prakash Narayanan, Rubin A. Parekhji
2017Using piecewise-functional broadside tests for functional broadside test compaction.Irith Pomeranz
2017Fail data reduction for diagnosis of scan chain faults under transparent-scan.Irith Pomeranz
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