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IEEE VLSI Test Symposium

VTS

National

CORE rank

CORE rank (raw)

National/Regional

Fields of research

Computer Systems Engineering

Papers indexed

2,208

1991–2026

Papers per year

199189 peak2026

VTS papers

2,208 records sourced from DBLP. Search titles, filter by year, sort by recency.

YearTitleAuthors
2015Impact of parameter variations on FinFET faults.Gurgen Harutyunyan, Grigor Tshagharyan, Yervant Zorian
2015Pulse shrinkage based pre-bond through silicon vias test in 3D IC.Chang Hao, Huaguo Liang
2015Testing cross wire opens within complex gates.Chao Han, Adit D. Singh
2015An early prediction methodology for aging sensor insertion to assure safe circuit operation due to NBTI aging.Andres F. Gomez, Leticia B. Poehls, Fabian Vargas, Vctor H. Champac
2015Abstraction-based relation mining for functional test generation.Kelson Gent, Michael S. Hsiao
2015Horizontal-FPN fault coverage improvement in production test of CMOS imagers.Richun Fei, Jocelyn Moreau, Salvador Mir, Alexis Marcellin, C. Mandier, E. Huss, G. Palmigiani, P. Vitrou, Thomas Droniou
2015Multi-cycle Circuit Parameter Independent ATPG for interconnect open defects.Dominik Erb, Karsten Scheibler, Matthias Sauer, Sudhakar M. Reddy, Bernd Becker
2015Capacitive Coupling Mitigation for TSV-based 3D ICs.Ashkan Eghbal, Pooria M. Yaghini, Nader Bagherzadeh
2015A call to action: Securing IEEE 1687 and the need for an IEEE test Security Standard.Jennifer Dworak, Al Crouch
20153D microelectronic with BEOL compatible devices.Dominique Drouin, Mohamed Amine-Bounouar, Gabriel Droulers, M. Labalette, Michel Pioro-Ladriere, A. Souifi, Serge Ecoffey
2015Field, experimental, and analytical data on large-scale HPC systems and evaluation of the implications for exascale system design.Nathan DeBardeleben, Sean Blanchard, David R. Kaeli, Paolo Rech
2015Automated testing of mixed-signal integrated circuits by topology modification.Anthony Coyette, Baris Esen, Ronny Vanhooren, Wim Dobbelaere, Georges G. E. Gielen
2015Fault modeling and testing of 1T1R memristor memories.Yong-Xiao Chen, Jin-Fu Li
2015Statistical techniques for predicting system-level failure using stress-test data.Harry H. Chen, Shih-Hua Kuo, Jonathan Tung, Mango Chia-Tso Chao
2015PPB: Partially-working processors binning for maximizing wafer utilization.Da Cheng, Sandeep K. Gupta
2015Ultrafast stimulus error removal algorithm for ADC linearity test.Tao Chen, Degang Chen
2015Enabling unauthorized RF transmission below noise floor with no detectable impact on primary communication performance.Doohwang Chang, Bertan Bakkaloglu, Sule Ozev
2015Panel: When will the cost of dependability end innovation in computer design?Valeria Bertacco
2015Disturbance-free BIST for loop characterization of DC-DC buck converters.Navankur Beohar, Priyanka Bakliwal, Sidhanto Roy, Debashis Mandal, Philippe Adell, Bert Vermeire, Bertan Bakkaloglu, Sule Ozev
2015Special session: Hot topics: Statistical test methods.Manuel J. Barragn, Gildas Lger, Florence Azas, Ronald D. Blanton, Adit D. Singh, Stephen Sunter
2015Innovative practices session 5C: Advancements in test -keeping moore moving!M. Enamul Amyeen
2015TMO: A new class of attack on cipher misusing test infrastructure.Sk Subidh Ali, Ozgur Sinanoglu
2015Resiliency challenges in sub-10nm technologies.Rob Aitken, Ethan H. Cannon, Mondira Pant, Mehdi Baradaran Tahoori
2015Panel: Is design-for-security the new DFT?Rob Aitken
2015Yield prognosis for fab-to-fab product migration.Ali Ahmadi, Ke Huang, Amit Nahar, Bob Orr, Michael Pas, John M. Carulli, Yiorgos Makris
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