| 2015 | Integral impact of BTI and voltage temperature variation on SRAM sense amplifier. | Innocent Agbo, Mottaqiallah Taouil, Said Hamdioui, Halil Kukner, Pieter Weckx, Praveen Raghavan, Francky Catthoor |
| 2014 | Improved power supply noise control for pseudo functional test. | Tengteng Zhang, Duncan M. Hank Walker |
| 2014 | On-chip voltage-droop prediction using support-vector machines. | Fangming Ye, Farshad Firouzi, Yang Yang, Krishnendu Chakrabarty, Mehdi Baradaran Tahoori |
| 2014 | A 4-GHz universal high-frequency on-chip testing platform for IP validation. | Ping-Lin Yang, Cheng-Chung Lin, Ming-Zhang Kuo, Sang-Hoo Dhong, Chien-Min Lin, Kevin Huang, Ching-Nen Peng, Min-Jer Wang |
| 2014 | Testing methods for a write-assist disturbance-free dual-port SRAM. | Hao-Yu Yang, Chen-Wei Lin, Chao-Ying Huang, Ching-Ho Lu, Chen-An Lai, Mango Chia-Tso Chao, Rei-Fu Huang |
| 2014 | Accurate and efficient method of jitter and noise separation and its application to ADC testing. | Li Xu, Degang Chen |
| 2014 | An efficient diagnosis method to deal with multiple fault-pairs simultaneously using a single circuit model. | Cheng-Hung Wu, Kuen-Jong Lee, Wei-Cheng Lien |
| 2014 | A built-in gain calibration technique for RF low-noise amplifiers. | Ya-Ru Wu, Yi-Keng Hsieh, Po-Chih Ku, Liang-Hung Lu |
| 2014 | Power/ground supply voltage variation-aware delay test pattern generation. | Lu Wang, Xutao Wang, Milad Maleki, Bao Liu |
| 2014 | Alternative "safe" test of hysteretic power converters. | Xian Wang, Blanchard Kenfack, Estella Silva, Abhijit Chatterjee |
| 2014 | At-speed interconnect testing and test-path optimization for 2.5D ICs. | Ran Wang, Krishnendu Chakrabarty, Sudipta Bhawmik |
| 2014 | SMV methodology enhancements for high speed I/O links of SoCs. | Andres Viveros-Wacher, Ricardo Alejos, Liliana Alvarez, Israel Diaz-Castro, Brenda Marcial, Gaston Motola-Acuna, Edgar-Andrei Vega-Ochoa |
| 2014 | Quality versus cost analysis for 3D Stacked ICs. | Mottaqiallah Taouil, Said Hamdioui, Erik Jan Marinissen |
| 2014 | Innovative practices session 7C: Reduced pin-count testing - How low can we go? | Stephen K. Sunter, Steve Comen, Paul Berndt, Ram Rajamani |
| 2014 | Efficient Monte Carlo-based analog parametric fault modelling. | Haralampos-G. D. Stratigopoulos, Stephen Sunter |
| 2014 | Functional block extraction for hardware security detection using time-integrated and time-resolved emission measurements. | Franco Stellari, Peilin Song, Herschel A. Ainspan |
| 2014 | Modeling location based wafer die yield variation in estimating 3D stacked IC yield from wafer to wafer stacking. | Eshan Singh |
| 2014 | Test planning and test access mechanism design for stacked chips using ILP. | Breeta SenGupta, Erik Larsson |
| 2014 | Special session 12C: Young professionals in test - Town meeting. | Alodeep Sanyal, Yanjing Li, Yervant Zorian |
| 2014 | Special session 11C: Young professionals in test - Elevator talks. | Alodeep Sanyal, Yanjing Li |
| 2014 | Fault tolerant nanoarray circuits: Automatic design and verification. | Pasquale Ranone, Giovanna Turvani, Fabrizio Riente, Mariagrazia Graziano, Massimo Ruo Roch, Maurizio Zamboni |
| 2014 | Special session 8A: E.J. McCluskey Doctoral Thesis Award semi-final. | Michele Portolan, Michail Maniatakos |
| 2014 | On the use of multi-cycle tests for storage of two-cycle broadside tests. | Irith Pomeranz |
| 2014 | Fault simulation with test switching for static test compaction. | Irith Pomeranz |
| 2014 | Special session 4B: Panel: Testing and calibration for power management circuits. | Sule Ozev, Bertan Bakkaloglu |