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IEEE VLSI Test Symposium

VTS

National

CORE rank

CORE rank (raw)

National/Regional

Fields of research

Computer Systems Engineering

Papers indexed

2,208

1991–2026

Papers per year

199189 peak2026

VTS papers

2,208 records sourced from DBLP. Search titles, filter by year, sort by recency.

YearTitleAuthors
2013Innovative practices session 3C: Harnessing the challenges of testability and debug of high speed I/Os.Saghir A. Shaikh
2013Innovative practices session 9C: Yield improvement: Challenges and directions.B. Seshadri, Bruce Cory, S. Mitra
2013Combining checkpointing and scrubbing in FPGA-based real-time systems.Aitzan Sari, Mihalis Psarakis, Dimitris Gizopoulos
2013Special session 12C: Town-hall meeting "young professionals in test".Alodeep Sanyal, Yervant Zorian
2013Identification of critical variables using an FPGA-based fault injection framework.Andreas Riefert, Jrg Mller, Matthias Sauer, Wolfram Burgard, Bernd Becker
2013Contactless test access mechanism for TSV based 3D ICs.Rashid Rashidzadeh
2013Scalable dynamic technique for accurately predicting power-supply noise and path delay.Sushmita Kadiyala Rao, Ryan W. Robucci, Chintan Patel
2013Special session 3B: E.J. McCluskey Doctoral Thesis Award semi-final - Posters.Michele Portolan, Michail Maniatakos
2013Special session 8A: E.J. McCluskey doctoral thesis award semi-final - presentations.Michele Portolan, Michail Maniatakos
2013Special session 12A: Hot topic counterfeit IC identification: How can test help?Ilia Polian, Mohammad Tehranipoor
2013A multi-faceted approach to FPGA-based Trojan circuit detection.Michael Patterson, Aaron Mills, Ryan A. Scheel, Julie Tillman, Evan Dye, Joseph Zambreno
2013Towards a cost-effective hardware trojan detection methodology.Raymond Paseman, Alex Orailoglu
2013An iterative diagnosis approach for ECC-based memory repair.Panagiota Papavramidou, Michael Nicolaidis
2013Innovative practices session 10C: Delay test.P. Pant, M. Amodeo, Sujal Vora, Jonathon E. Colburn
2013Post-DfT-insertion retiming for delay recovery on inter-die paths in 3D ICs.Brandon Noia, Krishnendu Chakrabarty
2013Innovative practices session 5C: Cloud atlas - Unreliability through massive connectivity.Helia Naeimi, Suriya Natarajan, Kushagra Vaid, Prabhakar Kudva, Mahesh Natu
2013SOC test compression scheme using sequential linear decompressors with retained free variables.Sreenivaas S. Muthyala, Nur A. Touba
2013RAVAGE: Post-silicon validation of mixed signal systems using genetic stimulus evolution and model tuning.Barry John Muldrey, Sabyasachi Deyati, Michael Giardino, Abhijit Chatterjee
2013Low-cost multi-channel testing of periodic signals using monobit receivers and incoherent subsampling.Thomas Moon, Hyun Woo Choi, Abhijit Chatterjee
2013An IDDQ BIST approach to characterize phase-locked loop parameters.Samed Maltabas, Osman Kubilay Ekekon, Kemal Kulovic, Anne Meixner, Martin Margala
2013Special session 4C: Hot topic 3D-IC design and test.Jin-Fu Li, Cheng-Wen Wu, Masahiro Aoyagi, Meng-Fan Marvin Chang, Ding-Ming Kwai
2013Testing of a low-VMIN data-aware dynamic-supply 8T SRAM.Chen-Wei Lin, Chin-Yuan Huang, Mango Chia-Tso Chao
2013Investigation of gate oxide short in FinFETs and the test methods for FinFET SRAMs.Chen-Wei Lin, Mango Chia-Tso Chao, Chih-Chieh Hsu
2013Special session 9B: Embedded tutorial embedded DfT instrumentation: Design, access, retargeting and case studies.Erik Larsson
2013Reduced code linearity testing of pipeline adcs in the presence of noise.Asma Laraba, Haralampos-G. D. Stratigopoulos, Salvador Mir, Herv Naudet, Gerard Bret
726750 of 2,208← PreviousNext →

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