Skip to content

IEEE VLSI Test Symposium

VTS

National

CORE rank

CORE rank (raw)

National/Regional

Fields of research

Computer Systems Engineering

Papers indexed

2,208

1991–2026

Papers per year

199189 peak2026

VTS papers

2,208 records sourced from DBLP. Search titles, filter by year, sort by recency.

YearTitleAuthors
2010Test cost and test power conflicts: EDA perspective.Mokhtar Hirech
2010Fast path selection for testing of small delay defects considering path correlations.Zijian He, Tao Lv, Huawei Li, Xiaowei Li
2010Special session 8B: New topic MOS/MTJ-hybrid circuit with nonvolatile logic-in-memory architecture and its impact.Takahiro Hanyu
2010Innovative practices session 5C: Post-silicon debug.Smriti Gupta
2010Reusing NoC-infrastructure for test data compression.Viktor Froese, Rdiger Ibers, Sybille Hellebrand
2010Detecting NBTI induced failures in SRAM core-cells.Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine
2010Concurrent process model and specification cause-effect monitoring using alternate diagnostic signatures.Shyam Kumar Devarakond, Shreyas Sen, Soumendu Bhattacharya, Abhijit Chatterjee
20103D self testing with Spidergon STNoC.Marcello Coppola
2010iMajik: Making 1149.1 TAPs disappear and reappear in SoCs and 3D packages.Christopher J. Clark
2010Reducing test time and area overhead of an embedded memory array built-in repair analyzer with optimal repair rate.Jaeyong Chung, Joonsung Park, Jacob A. Abraham, Eonjo Byun, Cheol-Jong Woo
2010Identification of critical primitive path delay faults without any path enumeration.Kyriakos Christou, Maria K. Michael, Stelios Neophytou
2010Power delivery dynamics and its impact on silicon validation.Eli Chiprout
2010Selecting the most relevant structural Fmax for system Fmax correlation.Janine Chen, Jing Zeng, Li-C. Wang, Jeff Rearick, Michael Mateja
2010Low-capture-power at-speed testing using partial launch-on-capture test scheme.Zhen Chen, Dong Xiang
2010On-chip testing of blind and open-sleeve TSVs for 3D IC before bonding.Po-Yuan Chen, Cheng-Wen Wu, Ding-Ming Kwai
2010A novel hybrid delay testing scheme with low test power, volume, and time.Zhen Chen, Sharad C. Seth, Dong Xiang
2010VDDmin test optimization for overscreening minimization through adaptive scan chain masking.Mingjing Chen, Alex Orailoglu
2010Design, analysis, and test of low-power and reliable flexible electronics.Kwang-Ting Cheng, Tsung-Ching Huang
2010Innovative practices session 2C: Design, fabrication and test of flexible electronics.Kwang-Ting Cheng
2010Low cost test and tuning of RF circuits and systems.Abhijit Chatterjee, Friedrich Taenzler
2010Calibration-assisted production testing for digitally-calibrated ADCs.Hsiu-Ming Chang, Kuan-Yu Lin, Kwang-Ting Cheng
2010Special session 11C: Hot topic design consideration and silicon evaluation of on-chip monitors.Sreejit Chakravarty
2010Special session 11B: Hot topic hardware security: Design, test and verification issues.Swarup Bhunia, Anand Raghunathan
2010Low power compression architecture.Sandeep Bhatia
2010Adaptive test delivers wide range of sophisticated test solutions.K. Arnold
951975 of 2,208← PreviousNext →

Comparable venues

Other A*/A conferences filed under the same field of research.