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IEEE VLSI Test Symposium

VTS

National

CORE rank

CORE rank (raw)

National/Regional

Fields of research

Computer Systems Engineering

Papers indexed

2,208

1991–2026

Papers per year

199189 peak2026

VTS papers

2,208 records sourced from DBLP. Search titles, filter by year, sort by recency.

YearTitleAuthors
2010Power noise and its impact on production test and validation of SoC devices.Karim Arabi
2010Special session 6C: New topic mixed-signal test impact to SoC commercialization.Karim Arabi
2010Ordering of analog specification tests based on parametric defect level estimation.Nourredine Akkouche, Salvador Mir, Emmanuel Simeu
2010Reliable cache design with on-chip monitoring of NBTI degradation in SRAM cells using BIST.Fahad Ahmed, Linda Milor
2009Efficient Array Characterization in the UltraSPARC T2.Thomas A. Ziaja, Poh J. Tan
2009On-Line Calibration and Power Optimization of RF Systems Using a Built-In Detector.Chaoming Zhang, Ranjit Gharpurey, Jacob A. Abraham
2009Controlling DPPM through Volume Diagnosis.Xiaochun Yu, Yen-Tzu Lin, Wing Chiu Tam, Osei Poku, Ronald D. Blanton
2009A Synthesis Method to Alleviate Over-Testing of Delay Faults Based on RTL Don't Care Path Identification.Yuki Yoshikawa, Satoshi Ohtake, Tomoo Inoue, Hideo Fujiwara
2009Automated Selection of Signals to Observe for Efficient Silicon Debug.Joon-Sung Yang, Nur A. Touba
2009Design-for-Testability for Digital Microfluidic Biochips.Tao Xu, Krishnendu Chakrabarty
2009False Path Aware Timing Yield Estimation under Variability.Lin Xie, Azadeh Davoodi, Kewal K. Saluja, Abhishek A. Sinkar
2009Dynamic Test Compaction for Transition Faults in Broadside Scan Testing Based on an Influence Cone Measure.Dong Xiang, Boxue Yin, Kwang-Ting Cheng
2009Compact Delay Test Generation with a Realistic Low Cost Fault Coverage Metric.Zheng Wang, Duncan M. Hank Walker
2009Analytical Model for Multi-site Efficiency with Parallel to Serial Test Times, Yield and Clustering.Naveen Velamati, Robert Daasch
2009Stuck-Open Fault Leakage and Testing in Nanometer Technologies.Julio Csar Vzquez, Vctor H. Champac, Chuck Hawkins, Jaume Segura
2009Bridging DFM Analysis and Volume Diagnostics for Yield Learning - A Case Study.Ritesh P. Turakhia, Mark Ward, Sandeep Kumar Goel, Brady Benware
2009Multiple-Fault Diagnosis Using Faulty-Region Identification.Meng-Jai Tasi, Mango Chia-Tso Chao, Jing-Yang Jou, Meng-Chen Wu
2009Predictive Test Technique for Diagnosis of RF CMOS Receivers.Kay Suenaga, Sebasti A. Bota, Rodrigo Picos, Eugeni Isern, Miquel Roca, Eugenio Garca-Moreno
2009Panel: Analog Characterization and Test: The Long Road to Realization.Arani Sinha, Amitava Majumdar, Vasu Ganti
2009Yield and Cost Analysis of a Reliable NoC.Saeed Shamshiri, Kwang-Ting Cheng
2009Panel: Functional Verification Planning and Management - Are Good Intentions Good Enough?Andrew Piziali
2009Understanding Power Supply Droop during At-Speed Scan Testing.Pankaj Pant, Joshua Zelman
2009Highly X-Tolerant Selective Compaction of Test Responses.Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Dariusz Czysz, Jerzy Tyszer
2009Output Hazard-Free Transition Delay Fault Test Generation.Sreekumar Menon, Adit D. Singh, Vishwani D. Agrawal
2009Automated Debug of Speed Path Failures Using Functional Tests.Richard McLaughlin, Srikanth Venkataraman, Carlston Lim
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