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IEEE VLSI Test Symposium

VTS

National

CORE rank

CORE rank (raw)

National/Regional

Fields of research

Computer Systems Engineering

Papers indexed

2,208

1991–2026

Papers per year

199189 peak2026

VTS papers

2,208 records sourced from DBLP. Search titles, filter by year, sort by recency.

YearTitleAuthors
2009Instruction-Level Impact Comparison of RT- vs. Gate-Level Faults in a Modern Microprocessor Controller.Michail Maniatakos, Naghmeh Karimi, Chandra Tirumurti, Abhijit Jas, Yiorgos Makris
2009Layout-Aware Pattern Generation for Maximizing Supply Noise Effects on Critical Paths.Junxia Ma, Jeremy Lee, Mohammad Tehranipoor
2009Special Session 7C: TTTC 2009 Best Doctoral Thesis Contest.Yiorgos Makris, Haralampos-G. D. Stratigopoulos
2009Automatic Selection of Internal Observation Signals for Design Verification.Tao Lv, Huawei Li, Xiaowei Li
2009Experimental Validation of a BIST Techcnique for CMOS Active Pixel Sensors.Livier Lizarraga, Salvador Mir, Gilles Sicard
2009Soft-Error Hardening Designs of Nanoscale CMOS Latches.Sheng Lin, Yong-Bin Kim, Fabrizio Lombardi
2009Physically-Aware N-Detect Test Relaxation.Yen-Tzu Lin, Chukwuemeka U. Ezekwe, Ronald D. Blanton
2009DFT and Test Problems from the Trenches.Haluk Konuk
2009Defect Detection Differences between Launch-Off-Shift and Launch-Off-Capture in Sense-Amplifier-Based Flip-Flop Testing.Haluk Konuk
2009Panel: Apprentice - VTS Edition: Season 2.Kee Sup Kim
2009STDF Memory Fail Datalog Standard.Ajay Khoche, Jay Katz, Sauro Landini, Kochen Liao, Neetu Agrawal, Glenn Plowman, Songlin Zuo, Liyang Lai, John Rowe, Thomas Zanon
2009Special Session 11C: Embedded Tutorial: System-on-a-Chip Power Management Implications on Validation and Testing.Bhanu Kapoor
2009A Scalable, Digital BIST Circuit for Measurement and Compensation of Static Phase Offset.Keith A. Jenkins, Lionel Li
2009Modeling and Testing Comparison Faults of TCAMs with Asymmetric Cells.Yong-Jyun Hu, Yu-Jen Huang, Jin-Fu Li
2009An Electrical Model for the Fault Simulation of Small Delay Faults Caused by Crosstalk Aggravated Resistive Short Defects.Nicolas Houarche, Mariane Comte, Michel Renovell, Alejandro Czutro, Piet Engelke, Ilia Polian, Bernd Becker
2009Restrict Encoding for Mixed-Mode BIST.Abdul Wahid Hakmi, Stefan Holst, Hans-Joachim Wunderlich, Jrgen Schlffel, Friedrich Hapke, Andreas Glowatz
2009Effective and Efficient Test Pattern Generation for Small Delay Defect.Sandeep Kumar Goel, Narendra Devta-Prasanna, Ritesh P. Turakhia
2009A New Post-Silicon Debug Approach Based on Suspect Window.Jianliang Gao, Yinhe Han, Xiaowei Li
2009Scalable Compact Test Pattern Generation for Path Delay Faults Based on Functions.Edward Flanigan, Spyros Tragoudas, Arkan Abdulrahman
2009RT-Level Deviation-Based Grading of Functional Test Sequences.Hongxia Fang, Krishnendu Chakrabarty, Abhijit Jas, Srinivas Patil, Chandra Tirumurti
2009A Packet Based 2x-Site Test Solution for GSM Transceivers with Limited Tester Resources.Erdem Serkan Erdogan, Sule Ozev
2009Exploiting Unused Spare Columns to Improve Memory ECC.Rudrajit Datta, Nur A. Touba
2009Special Session 8: New Topics: At-Speed Testing in the Face of Process Variations.Bernard Courtois, Chandu Visweswariah
2009Microscale and Nanoscale Thermal Characterization of Integrated Circuit Chips.Bernard Courtois, Ali Shakouri
2009A High-Level Signal Integrity Fault Model and Test Methodology for Long On-Chip Interconnections.Sunghoon Chun, YongJoon Kim, Taejin Kim, Sungho Kang
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