| 2009 | Efficient Scheduling of Path Delay Tests for Latch-Based Circuits. | Kun Young Chung, Sandeep K. Gupta |
| 2009 | Recursive Path Selection for Delay Fault Testing. | Jaeyong Chung, Jacob A. Abraham |
| 2009 | The ATPG Conflict-Driven Scheme for High Transition Fault Coverage and Low Test Cost. | Zhen Chen, Dong Xiang, Boxue Yin |
| 2009 | An Adaptive-Rate Error Correction Scheme for NAND Flash Memory. | Te-Hsuan Chen, Yu-Ying Hsiao, Yu-Tsao Hsing, Cheng-Wen Wu |
| 2009 | Calibration and Testing Time Reduction Techniques for a Digitally-Calibrated Pipelined ADC. | Hsiu-Ming Chang, Chin-Hsuan Chen, Kuan-Yu Lin, Kwang-Ting Cheng |
| 2009 | SS-KTC: A High-Testability Low-Overhead Scan Architecture with Multi-level Security Integration. | Unni Chandran, Dan Zhao |
| 2009 | Characterization of Effective Laser Spots during Attacks in the Configuration of a Virtex-II FPGA. | Gaetan Canivet, Rgis Leveugle, Jessy Cldire, Frdric Valette, Marc Renaudin |
| 2009 | A Time Domain Method to Measure Oscillator Phase Noise. | Kenneth Blakkan, Mani Soma |
| 2009 | Maintaining Accuracy of Test Compaction through Adaptive Re-learning. | Sounil Biswas, Ronald D. Blanton |
| 2009 | Testing for Transistor Aging. | A. Hakan Baba, Subhasish Mitra |
| 2009 | Small Delay Fault Model for Intra-Gate Resistive Open Defects. | Masayuki Arai, Akifumi Suto, Kazuhiko Iwasaki, Katsuyuki Nakano, Michihiro Shintani, Kazumi Hatayama, Takashi Aikyo |
| 2009 | DfT Reuse for Low-Cost Radiation Testing of SoCs: A Case Study. | Davide Appello, Paolo Bernardi, Simone Gerardin, Michelangelo Grosso, Alessandro Paccagnella, Paolo Rech, Matteo Sonza Reorda |
| 2008 | Codeword Selection for Crosstalk Avoidance and Error Correction on Interconnects. | Ying Zhang, Huawei Li, Xiaowei Li, Yu Hu |
| 2008 | Multiple Coupling Effects Oriented Path Delay Test Generation. | Minjin Zhang, Huawei Li, Xiaowei Li |
| 2008 | Low Cost RF Receiver Parameter Measurement with On-Chip Amplitude Detectors. | Chaoming Zhang, Ranjit Gharpurey, Jacob A. Abraham |
| 2008 | Test-Pattern Grading and Pattern Selection for Small-Delay Defects. | Mahmut Yilmaz, Krishnendu Chakrabarty, Mohammad Tehranipoor |
| 2008 | A General Failure Candidate Ranking Framework for Silicon Debug. | Chia-Chih Yen, Ten Lin, Hermes Lin, Kai Yang, Ta-Yung Liu, Yu-Chin Hsu |
| 2008 | Expanding Trace Buffer Observation Window for In-System Silicon Debug through Selective Capture. | Joon-Sung Yang, Nur A. Touba |
| 2008 | On the Detectability of Scan Chain Internal Faults - An Industrial Case Study. | Fan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz |
| 2008 | Scan-Chain Reordering for Minimizing Scan-Shift Power Based on Non-Specified Test Cubes. | Yu-Ze Wu, Mango Chia-Tso Chao |
| 2008 | Dynamic Compaction for High Quality Delay Test. | Zheng Wang, D. M. H. Walker |
| 2008 | An All-Digital High-Precision Built-In Delay Time Measurement Circuit. | Ming-Chien Tsai, Ching-Hwa Cheng, Chiou-Mao Yang |
| 2008 | A Regression Based Technique for ATE-Aware Test Data Volume Estimation of System-on-Chips. | Rajesh Tiwari, Abhijeet Shrivastava, Mahit Warhadpande, Srivaths Ravi, Rubin A. Parekhji |
| 2008 | Fast Measurement of the "Non-Deterministic Zone" in Microprocessor Debug Using Maximum Likelihood Estimation. | Desta Tadesse, R. Iris Bahar, Joel Grodstein |
| 2008 | Automatic Test Pattern Generation for Interconnect Open Defects. | Stefan Spinner, Ilia Polian, Piet Engelke, Bernd Becker, Martin Keim, Wu-Tung Cheng |