IEEE VLSI Test Symposium

VTS

National

CORE rank

CORE rank (raw)

National/Regional

Fields of research

Computer Systems Engineering

Papers indexed

2,208

1991–2026

Best Computer Systems Engineering conferences

Papers per year

199189 peak2026

Most published authors

VTS papers

2,208 records sourced from DBLP. Search titles, filter by year, sort by recency.

Year	Title	Authors
2008	Constructing Augmented Multimode Compactors.	Emil Gizdarski
2008	Increasing Output Compaction in Presence of Unknowns Using an X-Canceling MISR with Deterministic Observation.	Ritesh Garg, Richard Putman, Nur A. Touba
2008	How Many Test Patterns are Useless?	Franois-Fabien Ferhani, Nirmal R. Saxena, Edward J. McCluskey, Phil Nigh
2008	Single-Measurement Diagnostic Test Method for Parametric Faults of I/Q Modulating RF Transceivers.	Erdem Serkan Erdogan, Sule Ozev
2008	Low-cost Test of Timing Mismatch Among Time-Interleaved A/D Converters in High-speed Communication Systems.	Qingqi Dou, Jacob A. Abraham
2008	A Statistical Approach to Characterizing and Testing Functionalized Nanowires.	James Dardig, Haralampos-G. D. Stratigopoulos, Eric Stern, Mark A. Reed, Yiorgos Makris
2008	An Efficient Scan Chain Diagnosis Method Using a New Symbolic Simulation.	Sunghoon Chun, Taejin Kim, YongJoon Kim, Sungho Kang
2008	A Novel SBST Generation Technique for Path-Delay Faults in Microprocessors Exploiting Gate- and RT-Level Descriptions.	Kyriakos Christou, Maria K. Michael, Paolo Bernardi, Michelangelo Grosso, Ernesto Snchez, Matteo Sonza Reorda
2008	QBIST: Quantum Built-in Self-Test for any Boolean Circuit.	Yao-Hsin Chou, Sy-Yen Kuo, I-Ming Tsai
2008	Gate-Oxide Early Life Failure Prediction.	Tze Wee Chen, Kyunglok Kim, Young Moon Kim, Subhasish Mitra
2008	Bounded Adjacent Fill for Low Capture Power Scan Testing.	Anshuman Chandra, Rohit Kapur
2008	Test Compaction for Mixed-Signal Circuits Using Pass-Fail Test Data.	Sounil Biswas, R. D. (Shawn) Blanton
2008	Test-Pattern Ordering for Wafer-Level Test-During-Burn-In.	Sudarshan Bahukudumbi, Krishnendu Chakrabarty
2008	Full Open Defects in Nanometric CMOS.	Daniel Arum, Rosa Rodrguez-Montas, Joan Figueras, Stefan Eichenberger, Camelia Hora, Bram Kruseman
2008	Signature Rollback - A Technique for Testing Robust Circuits.	Uranmandakh Amgalan, Christian Hachmann, Sybille Hellebrand, Hans-Joachim Wunderlich
2008	Reducing Scan Shift Power at RTL.	Elif Alpaslan, Yu Huang, Xijiang Lin, Wu-Tung Cheng, Jennifer Dworak
2007	Speeding Up Effect-Cause Defect Diagnosis Using a Small Dictionary.	Wei Zou, Wu-Tung Cheng, Sudhakar M. Reddy, Huaxing Tang
2007	Using Domain Partitioning in Wrapper Design for IP Cores Under Power Constraints.	Thomas Edison Yu, Tomokazu Yoneda, Danella Zhao, Hideo Fujiwara
2007	TAM Design and Optimization for Transparency-Based SoC Test.	Tomokazu Yoneda, Akiko Shuto, Hideyuki Ichihara, Tomoo Inoue, Hideo Fujiwara
2007	Automated Design and Insertion of Optimal One-Hot Bus Encoders.	Peter Wohl, John A. Waicukauski, Sanjay Patel
2007	Minimizing the Impact of Scan Compression.	Peter Wohl, John A. Waicukauski, Rohit Kapur, Sanjay Ramnath, Emil Gizdarski, Thomas W. Williams, P. Jaini
2007	Parameter Estimation for a Model with Both Imperfect Test and Repair.	Simon P. Wilson, Ben Flood, Suresh Goyal, Jim Mosher, Susan Bergin, Joseph O'Brien, Robert Kennedy
2007	Using Scan-Dump Values to Improve Functional-Diagnosis Methodology.	Vishnu C. Vimjam, M. Enamul Amyeen, Ruifeng Guo, Srikanth Venkataraman, Michael S. Hsiao, Kai Yang
2007	At-Speed Testing of Core-Based System-on-Chip Using an Embedded Micro-Tester.	Matthieu Tuna, Mounir Benabdenbi, Alain Greiner
2007	A Built-In Self-Repair Scheme for Multiport RAMs.	Tsu-Wei Tseng, Chun-Hsien Wu, Yu-Jen Huang, Jin-Fu Li, Alex Pao, Kevin Chiu, Eliot Chen

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