| 2007 | A Low-Noise Amplifier with Integrated Current and Power Sensors for RF BIST Applications. | Yen-Chih Huang, Hsieh-Hung Hsieh, Liang-Hung Lu |
| 2007 | Using Clock-Vdd to Test and Diagnose the Power-Switch in Power-Gating Circuit. | Hsiang-Hui Huang, Ching-Hwa Cheng |
| 2007 | SDRAM Delay Fault Modeling and Performance Testing. | Yu-Tsao Hsing, Chun-Chieh Huang, Jen-Chieh Yeh, Cheng-Wen Wu |
| 2007 | A UML Based System Level Failure Rate Assessment Technique for SoC Designs. | Mohammad Hosseinabady, Mohammad Hossein Neishaburi, Pejman Lotfi-Kamran, Zainalabedin Navabi |
| 2007 | High Level Synthesis of Degradable ASICs Using Virtual Binding. | Nima Honarmand, Ali Shahabi, Hasan Sohofi, Maghsoud Abbaspour, Zainalabedin Navabi |
| 2007 | An Analysis Framework for Transient-Error Tolerance. | John P. Hayes, Ilia Polian, Bernd Becker |
| 2007 | Retention and Reliability Problems in Embedded Flash Memories: Analysis and Test of Defective 2T-FLOTOX Tunnel Window. | Olivier Ginez, Jean Michel Daga, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel |
| 2007 | An Analysis of Defect Detection for Weighted Random Patterns Generated with Observation/Excitation-Aware Partial Fault Targeting. | Jennifer Dworak |
| 2007 | Multiple Bit Upset Tolerant Memory Using a Selective Cycle Avoidance Based SEC-DED-DAEC Code. | Avijit Dutta, Nur A. Touba |
| 2007 | Glitch-Aware Pattern Generation and Optimization Framework for Power-Safe Scan Test. | V. R. Devanathan, C. P. Ravikumar, V. Kamakoti |
| 2007 | Low Power Embedded Deterministic Test. | Dariusz Czysz, Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer |
| 2007 | Test Set Reordering Using the Gate Exhaustive Test Metric. | Kyoung Youn Cho, Edward J. McCluskey |
| 2007 | Enhanced Resolution Jitter Testing Using Jitter Expansion. | Hyun Woo Choi, Donghoon Han, Abhijit Chatterjee |
| 2007 | Handling Pattern-Dependent Delay Faults in Diagnosis. | Jyun-Wei Chen, Ying-Yen Chen, Jing-Jia Liou |
| 2007 | Multimode Illinois Scan Architecture for Test Application Time and Test Data Volume Reduction. | Anshuman Chandra, Haihua Yan, Rohit Kapur |
| 2007 | Delay Test Quality Evaluation Using Bounded Gate Delays. | Soumitra Bose, Vishwani D. Agrawal |
| 2007 | RTL Test Point Insertion to Reduce Delay Test Volume. | Kedarnath J. Balakrishnan, Lei Fang |
| 2007 | Probabilistic Compensation for Digital Filters Using Pervasive Noise-Induced Operator Errors. | Maryam Ashouei, Soumendu Bhattacharya, Abhijit Chatterjee |
| 2007 | Diagnosis of Bridging Defects Based on Current Signatures at Low Power Supply Voltages. | Daniel Arum, Rosa Rodrguez-Montas, Joan Figueras, Stefan Eichenberger, Camelia Hora, Bram Kruseman, Maurice Lousberg, Ananta K. Majhi |
| 2007 | DfT for the Reuse of Networks-on-Chip as Test Access Mechanism. | Alexandre M. Amory, Frederico Ferlini, Marcelo Lubaszewski, Fernando Moraes |
| 2007 | Optimizing Test Length for Soft Faults in DRAM Devices. | Zaid Al-Ars, Said Hamdioui, Georgi Gaydadjiev |
| 2007 | Supply Voltage Noise Aware ATPG for Transition Delay Faults. | Nisar Ahmed, Mohammad Tehranipoor, Vinay Jayaram |
| 2007 | Circuit Failure Prediction and Its Application to Transistor Aging. | Mridul Agarwal, Bipul C. Paul, Ming Zhang, Subhasish Mitra |
| 2007 | Accelerating Diagnosis via Dominance Relations between Sets of Faults. | Rajsekhar Adapa, Spyros Tragoudas, Maria K. Michael |
| 2007 | A Low-Cost RF MIMO Test Method Using a Single Measurement Set-up. | Erkan Acar, Sule Ozev, Kevin B. Redmond |