| 2004 | Yield Analysis of Logic Circuits. | Davide Appello, Alessandra Fudoli, Katia Giarda, Emil Gizdarski, Ben Mathew, Vincenzo Tancorre |
| 2004 | Sensing temperature in CMOS circuits for Thermal Testing. | Josep Altet, Antonio Rubio, M. Amine Salhi, Jose Luis Glvez, Stefan Dilhaire, Ashish Syal, Andr Ivanov |
| 2004 | Cost-Driven Selection of Parity Trees. | Sobeeh Almukhaizim, Petros Drineas, Yiorgos Makris |
| 2004 | Effects of Bit Line Coupling on the Faulty Behavior of DRAMs. | Zaid Al-Ars, Said Hamdioui, Ad J. van de Goor |
| 2004 | Feature Extraction Based Built-In Alternate Test of RF Components Using a Noise Reference. | Selim Sermet Akbay, Abhijit Chatterjee |
| 2003 | SOC Test Scheduling Using Simulated Annealing. | Wei Zou, Sudhakar M. Reddy, Irith Pomeranz, Yu Huang |
| 2003 | Power Constrained Test Scheduling with Dynamically Varied TAM. | Dan Zhao, Shambhu J. Upadhyaya |
| 2003 | DSP-Based Statistical Self Test of On-Chip Converters. | Hak-soo Yu, Sungbae Hwang, Jacob A. Abraham |
| 2003 | Concurrent Execution of Diagnostic Fault Simulation and Equivalence Identification During Diagnostic Test Generation. | Xiaoming Yu, M. Enamul Amyeen, Srikanth Venkataraman, Ruifeng Guo, Irith Pomeranz |
| 2003 | Design for Consecutive Transparency of Cores in System-on-a-Chip. | Tomokazu Yoneda, Hideo Fujiwara |
| 2003 | Design for Self-Checking and Self-Timed Datapath. | Jing-Ling Yang, Oliver Chiu-sing Choy, Cheong-Fat Chan, Kong-Pang Pun |
| 2003 | Analysis and Design of Optimal Combinational Compactors. | Peter Wohl, Leendert M. Huisman |
| 2003 | Test and Diagnosis of Word-Oriented Multiport Memories. | Chih-Wea Wang, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu |
| 2003 | Efficient Seed Utilization for Reseeding based Compression. | Erik H. Volkerink, Subhasish Mitra |
| 2003 | Effectiveness of I-V Testing in Comparison to IDDq Tests. | Thomas J. Vogels |
| 2003 | Testing SoC Interconnects for Signal Integrity Using Boundary Scan. | Mohammad H. Tehranipour, Nisar Ahmed, Mehrdad Nourani |
| 2003 | Automatic Configuration Generation for FPGA Interconnect Testing. | Mehdi Baradaran Tahoori, Subhasish Mitra |
| 2003 | Efficient Implication - Based Untestable Bridge Fault Identifier. | Manan Syal, Michael S. Hsiao, Kiran B. Doreswamy, Sreejit Chakravarty |
| 2003 | 1149.4 Based On-Line Quiescent State Monitoring Technique. | Chauchin Su, Chih-Hu Wang, Wei-Juo Wang, I. S. Tseng |
| 2003 | Development of Energy Consumption Ratio Test. | Xiaoyun Sun, Larry L. Kinney, Bapiraju Vinnakota |
| 2003 | An Analog Checker with Dynamically Adjustable Error Threshold for Fully Differential Circuits. | Haralampos-G. D. Stratigopoulos, Yiorgos Makris |
| 2003 | Measurement of Phase and Frequency Variations in Radio-Frequency Signal. | Mani Soma, Welela Haileselassie, Jessica Sherrid |
| 2003 | Test Data Compression and Test Time Reduction of Longest-Path-Per-Gate Tests based on Illinois Scan Architecture. | Manish Sharma, Janak H. Patel, Jeff Rearick |
| 2003 | A Reconfigurable Shared Scan-in Architecture. | Samitha Samaranayake, Emil Gizdarski, Nodari Sitchinava, Frederic Neuveux, Rohit Kapur, Thomas W. Williams |
| 2003 | Use of Multiple IDDQ Test Metrics for Outlier Identification. | Sagar S. Sabade, D. M. H. Walker |