| 2003 | Embedded Tutorial: Test Consideration for Nanometer Scale CMOS Circuits. | Kaushik Roy, T. M. Mak, Kwang-Ting Cheng |
| 2003 | A Test Interface for Built-In Test of Non-Isolated Scanned Cores. | Irith Pomeranz, Sudhakar M. Reddy, Yervant Zorian |
| 2003 | On Maximizing the Fault Coverage for a Given Test Length Limit in a Synchronous Sequential Circuit. | Irith Pomeranz, Sudhakar M. Reddy |
| 2003 | Application of Saluja-Karpovsky Compactors to Test Responses with Many Unknowns. | Janak H. Patel, Steven S. Lumetta, Sudhakar M. Reddy |
| 2003 | Fault Testing for Reversible Circuits. | Ketan N. Patel, John P. Hayes, Igor L. Markov |
| 2003 | Ultra Low Cost Analog BIST Using Spectral Analysis. | Marcelo Negreiros, Luigi Carro, Altamiro Amadeu Susin |
| 2003 | An Embedded Autonomous Scan-Based Results Analyzer (EARA) for SoC Cores. | Mohsen Nahvi, Andr Ivanov |
| 2003 | High Speed Ring Generators and Compactors of Test Data. | Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer |
| 2003 | Eliminating Non-Determinism During Test of High-Speed Source Synchronous Differential Buses. | Kartik Mohanram, Nur A. Touba |
| 2003 | Improving Diagnostic Resolution of Delay Faults using Path Delay Fault Model. | Ananta K. Majhi, Guido Gronthoud, Camelia Hora, Maurice Lousberg, Pop Valer, Stefan Eichenberger |
| 2003 | Invited Keynote: Building Yield into Systems-on-Chips for Nanometer Technologies. | Philippe Magarshack |
| 2003 | A Circuit Level Fault Model for Resistive Opens and Bridges. | Zhuo Li, Xiang Lu, Wangqi Qiu, Weiping Shi, D. M. H. Walker |
| 2003 | Test Data Compression Using Dictionaries with Fixed-Length Indices. | Lei Li, Krishnendu Chakrabarty |
| 2003 | Test Resource Partitioning and Optimization for SOC Designs. | Erik Larsson, Hideo Fujiwara |
| 2003 | Diagnosis of Delay Defects Using Statistical Timing Models. | Angela Krstic, Li-C. Wang, Kwang-Ting Cheng, Jing-Jia Liou |
| 2003 | Testable Design and Testing of Micro-Electro-Fluidic Arrays. | Hans G. Kerkhoff, Mustafa Acar |
| 2003 | Built-In TPG with Designed Phaseshifts. | Dimitri Kagaris |
| 2003 | Design and Optimization of Multi-level TAM Architectures for Hierarchical SOCs. | Vikram Iyengar, Krishnendu Chakrabarty, Mark D. Krasniewski, Gopind N. Kumar |
| 2003 | Analyzing Crosstalk in the Presence of Weak Bridge Defects. | Shahdad Irajpour, Shahin Nazarian, Lei Wang, Sandeep K. Gupta, Melvin A. Breuer |
| 2003 | BIST-Aided Scan Test - A New Method for Test Cost Reduction. | Takahisa Hiraide, Kwame Osei Boateng, Hideaki Konishi, Koichi Itaya, Michiaki Emori, Hitoshi Yamanaka, Takashi Mochiyama |
| 2003 | Detecting Intra-Word Faults in Word-Oriented Memories. | Said Hamdioui, Ad J. van de Goor, Mike Rodgers |
| 2003 | Threshold Voltage Mismatch (DeltaVT) Fault Modeling. | Jos Pineda de Gyvez, Rosa Rodrguez-Montas |
| 2003 | Keynote Address. | Jon Fields |
| 2003 | An Efficient Test Relaxation Technique for Synchronous Sequential Circuits. | Aiman H. El-Maleh, Khaled Al-Utaibi |
| 2003 | The Impact of NoC Reuse on the Testing of Core-based Systems. | rika F. Cota, Mrcio Eduardo Kreutz, Cesar A. Zeferino, Luigi Carro, Marcelo Lubaszewski, Altamiro Amadeu Susin |