| 2003 | Layered Approach to Designing System Test Interfaces. | Man Wah Chiang, Zeljko Zilic |
| 2003 | Energy-Efficient Logic BIST Based on State Correlation Analysis. | Xiaoding Chen, Michael S. Hsiao |
| 2003 | Test Generation for Maximizing Ground Bounce Considering Circuit Delay. | Yi-Shing Chang, Sandeep K. Gupta, Melvin A. Breuer |
| 2003 | High Coverage Analog Wafer-Probe Test Design and Co-optimization with Assembled-Package Test to Minimize Overall Test Cost. | Soumendu Bhattacharya, Abhijit Chatterjee |
| 2003 | Effectiveness Comparisons of Outlier Screening Methods for Frequency Dependent Defects on Complex ASICs. | Brady Benware, Robert Madge, Cam Lu, W. Robert Daasch |
| 2003 | Decompression Hardware Determination for Test Volume and Time Reduction through Unified Test Pattern Compaction and Compression. | Ismet Bayraktaroglu, Alex Orailoglu |
| 2003 | Deterministic Test Vector Decompression in Software Using Linear Operations. | Kedarnath J. Balakrishnan, Nur A. Touba |
| 2003 | Bist Reseeding with very few Seeds. | Ahmad A. Al-Yamani, Subhasish Mitra, Edward J. McCluskey |
| 2003 | Built-In Reseeding for Serial Bist. | Ahmad A. Al-Yamani, Edward J. McCluskey |
| 2003 | Generating Complete and Optimal March Tests for Linked Faults in Memories. | Sultan M. Al-Harbi, Sandeep K. Gupta |
| 2003 | Path-Delay Fault Simulation for Circuits with Large Numbers of Paths for Very Large Test Sets. | Nabil M. Abdulrazzaq, Sandeep K. Gupta |
| 2003 | Transition Test Generation using Replicate-and-Reduce Transform for Scan-based Designs. | Magdy S. Abadir, Juhong Zhu |
| 2002 | Timing Jitter Measurement of 10 Gbps Bit Clock Signals Using Frequency Division. | Takahiro J. Yamaguchi, Masahiro Ishida, Mani Soma, Louis Malarsie, Hirobumi Musha |
| 2002 | Test Economics for Multi-site Test with Modern Cost Reduction Techniques. | Erik H. Volkerink, Ajay Khoche, Jochen Rivoir, Klaus-Dieter Hilliges |
| 2002 | Program Slicing for Hierarchical Test Generation. | Vivekananda M. Vedula, Jacob A. Abraham, Jayanta Bhadra |
| 2002 | Practical Solutions for the Application of the Oscillation-Based-Test: Start-Up and On-Chip Evaluation. | Diego Vzquez, Gloria Huertas, Gildas Lger, Adoracin Rueda, Jos L. Huertas |
| 2002 | Experimental Results for Slow-Speed Testing. | Chao-Wen Tseng, James Li, Edward J. McCluskey |
| 2002 | Speeding-Up IDDQ Measurements. | Claude Thibeault |
| 2002 | Novel Techniques for Achieving High At-Speed Transition Fault Test Coverage for Motorola's Microprocessors Based on PowerPC(tm) Instruction Set Architecture. | Nandu Tendolkar, Rajesh Raina, Rick Woltenberg, Xijiang Lin, Bruce Swanson, Greg Aldrich |
| 2002 | A Successful DFT Tester: What Will It Look Like? Is Revolution in Test Approaches Required? | Lee Song, Rudy Garcia, Andrew Levy, Donald L. Wheater |
| 2002 | Power Supply Transient Signal Analysis Under Real Process and Test Hardware Models. | Abhishek Singh, Jim Plusquellic, Anne E. Gattiker |
| 2002 | Test Power Reduction through Minimization of Scan Chain Transitions. | Ozgur Sinanoglu, Ismet Bayraktaroglu, Alex Orailoglu |
| 2002 | LI-BIST: A Low-Cost Self-Test Scheme for SoC Logic Cores and Interconnects. | Krishna Sekar, Sujit Dey |
| 2002 | Challenges in Nanometric Technology Scaling: Trends and Projections. | Jaume Segura, Vivek De, Ali Keshavarzi |
| 2002 | Test as a Key Enabler for Faster Yield Ramp-Up. | Julie Segal, Rene Segers, Rob Aitken, S. Eichenberge, A. Gattike, M. Millegen, R. Seger, S. Venkataraman |